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| author | Bartosz Nitka <niteria@gmail.com> | 2016-07-01 04:58:39 -0700 |
|---|---|---|
| committer | Bartosz Nitka <niteria@gmail.com> | 2016-07-01 05:44:27 -0700 |
| commit | cbfeff4b3caade8092c13f0f71371e6525ece9ac (patch) | |
| tree | 300101b60cea80cfd2640e4db74efdaa489b7cd9 /compiler/nativeGen/RegAlloc/Graph/Main.hs | |
| parent | 6377757918c1e7f63638d6f258cad8d5f02bb6a7 (diff) | |
| download | haskell-cbfeff4b3caade8092c13f0f71371e6525ece9ac.tar.gz | |
Remove uniqSetToList
This documents nondeterminism in code generation and removes
the nondeterministic ufmToList function. In the future someone
will have to use nonDetEltsUFM (with proper explanation)
or pprUFM.
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Graph/Main.hs')
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Graph/Main.hs | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/compiler/nativeGen/RegAlloc/Graph/Main.hs b/compiler/nativeGen/RegAlloc/Graph/Main.hs index 52ed438f81..f7b3d0179d 100644 --- a/compiler/nativeGen/RegAlloc/Graph/Main.hs +++ b/compiler/nativeGen/RegAlloc/Graph/Main.hs @@ -110,8 +110,11 @@ regAlloc_spin dflags spinCount triv regsFree slotsFree debug_codeGraphs code ( text "It looks like the register allocator is stuck in an infinite loop." $$ text "max cycles = " <> int maxSpinCount $$ text "regsFree = " <> (hcat $ punctuate space $ map ppr - $ uniqSetToList $ unionManyUniqSets - $ eltsUFM regsFree) + $ nonDetEltsUFM $ unionManyUniqSets + $ nonDetEltsUFM regsFree) + -- This is non-deterministic but we do not + -- currently support deterministic code-generation. + -- See Note [Unique Determinism and code generation] $$ text "slotsFree = " <> ppr (sizeUniqSet slotsFree)) -- Build the register conflict graph from the cmm code. @@ -312,15 +315,16 @@ graphAddConflictSet graphAddConflictSet set graph = let virtuals = mkUniqSet - [ vr | RegVirtual vr <- uniqSetToList set ] + [ vr | RegVirtual vr <- nonDetEltsUFM set ] graph1 = Color.addConflicts virtuals classOfVirtualReg graph graph2 = foldr (\(r1, r2) -> Color.addExclusion r1 classOfVirtualReg r2) graph1 [ (vr, rr) - | RegVirtual vr <- uniqSetToList set - , RegReal rr <- uniqSetToList set] + | RegVirtual vr <- nonDetEltsUFM set + , RegReal rr <- nonDetEltsUFM set] + -- See Note [Unique Determinism and code generation] in graph2 @@ -410,10 +414,11 @@ seqNode node = seqVirtualReg (Color.nodeId node) `seq` seqRegClass (Color.nodeClass node) `seq` seqMaybeRealReg (Color.nodeColor node) - `seq` (seqVirtualRegList (uniqSetToList (Color.nodeConflicts node))) - `seq` (seqRealRegList (uniqSetToList (Color.nodeExclusions node))) + `seq` (seqVirtualRegList (nonDetEltsUFM (Color.nodeConflicts node))) + `seq` (seqRealRegList (nonDetEltsUFM (Color.nodeExclusions node))) `seq` (seqRealRegList (Color.nodePreference node)) - `seq` (seqVirtualRegList (uniqSetToList (Color.nodeCoalesce node))) + `seq` (seqVirtualRegList (nonDetEltsUFM (Color.nodeCoalesce node))) + -- It's OK to use nonDetEltsUFM for seq seqVirtualReg :: VirtualReg -> () seqVirtualReg reg = reg `seq` () |