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authorbenl@ouroborus.net <unknown>2010-06-24 08:31:21 +0000
committerbenl@ouroborus.net <unknown>2010-06-24 08:31:21 +0000
commite1744771112465b5d43df1d7e38c8a7415b4705f (patch)
treeb60491b610116ac404a32fb845271d1116ce71ec /compiler/nativeGen/RegAlloc/Graph/Main.hs
parenta4e89052ca5163bc1a33b5096b50e5a3fbb9fbd5 (diff)
downloadhaskell-e1744771112465b5d43df1d7e38c8a7415b4705f.tar.gz
NCG: Comments and formatting only
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Graph/Main.hs')
-rw-r--r--compiler/nativeGen/RegAlloc/Graph/Main.hs8
1 files changed, 0 insertions, 8 deletions
diff --git a/compiler/nativeGen/RegAlloc/Graph/Main.hs b/compiler/nativeGen/RegAlloc/Graph/Main.hs
index 069c8c0069..cdbe98755a 100644
--- a/compiler/nativeGen/RegAlloc/Graph/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/Main.hs
@@ -43,7 +43,6 @@ maxSpinCount = 10
-- | The top level of the graph coloring register allocator.
---
regAlloc
:: (Outputable instr, Instruction instr)
=> DynFlags
@@ -169,9 +168,6 @@ regAlloc_spin
-- and rewrite SPILL/RELOAD pseudos into real instructions along the way
let code_final = map stripLive code_spillclean
--- let spillNatTop = mapGenBlockTop spillNatBlock
--- let code_final = map spillNatTop code_nat
-
-- record what happened in this stage for debugging
let stat =
RegAllocStatsColored
@@ -240,9 +236,7 @@ regAlloc_spin
code_relive
-
-- | Build a graph from the liveness and coalesce information in this code.
-
buildGraph
:: Instruction instr
=> [LiveCmmTop instr]
@@ -270,7 +264,6 @@ buildGraph code
-- | Add some conflict edges to the graph.
-- Conflicts between virtual and real regs are recorded as exclusions.
---
graphAddConflictSet
:: UniqSet Reg
-> Color.Graph VirtualReg RegClass RealReg
@@ -293,7 +286,6 @@ graphAddConflictSet set graph
-- | Add some coalesence edges to the graph
-- Coalesences between virtual and real regs are recorded as preferences.
---
graphAddCoalesce
:: (Reg, Reg)
-> Color.Graph VirtualReg RegClass RealReg