diff options
| author | Abhiroop Sarkar <asiamgenius@gmail.com> | 2018-09-27 15:28:46 -0400 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2019-07-01 17:02:29 -0400 |
| commit | ff823a08f897e770efda4e89c43618dc6e30bb65 (patch) | |
| tree | f26a80bcb060c8439d2daf8cefc9cb367bb3b388 /compiler/llvmGen/LlvmCodeGen/CodeGen.hs | |
| parent | bd660edeb783a74e5ca3f1f82713b2aeedae19dc (diff) | |
| download | haskell-wip/simd.tar.gz | |
Add support for SIMD operations in the NCGwip/simd
This adds support for constructing vector types from Float#, Double# etc
and performing arithmetic operations on them
Cleaned-Up-By: Ben Gamari <ben@well-typed.com>
Diffstat (limited to 'compiler/llvmGen/LlvmCodeGen/CodeGen.hs')
| -rw-r--r-- | compiler/llvmGen/LlvmCodeGen/CodeGen.hs | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs index 86a59381b2..8fea6e0b17 100644 --- a/compiler/llvmGen/LlvmCodeGen/CodeGen.hs +++ b/compiler/llvmGen/LlvmCodeGen/CodeGen.hs @@ -1287,6 +1287,7 @@ genMachOp _ op [x] = case op of MO_VU_Quot _ _ -> panicOp MO_VU_Rem _ _ -> panicOp + MO_VF_Broadcast _ _ -> panicOp MO_VF_Insert _ _ -> panicOp MO_VF_Extract _ _ -> panicOp @@ -1483,6 +1484,7 @@ genMachOp_slow opt op [x, y] = case op of MO_VS_Neg {} -> panicOp + MO_VF_Broadcast {} -> panicOp MO_VF_Insert {} -> panicOp MO_VF_Extract {} -> panicOp @@ -1844,9 +1846,9 @@ funEpilogue live = do let liveRegs = alwaysLive ++ live isSSE (FloatReg _) = True isSSE (DoubleReg _) = True - isSSE (XmmReg _) = True - isSSE (YmmReg _) = True - isSSE (ZmmReg _) = True + isSSE (XmmReg _ _ _ _) = True + isSSE (YmmReg _ _ _ _) = True + isSSE (ZmmReg _ _ _ _) = True isSSE _ = False -- Set to value or "undef" depending on whether the register is |