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| author | Simon Marlow <marlowsd@gmail.com> | 2011-04-18 12:14:19 +0100 |
|---|---|---|
| committer | Simon Marlow <marlowsd@gmail.com> | 2011-05-04 10:59:57 +0100 |
| commit | ac51be0997c4d0cf65cb3635b936ddf011e372bd (patch) | |
| tree | 0b1dccd096ffc1e4a67eb7239a19c3c5c27ba3a0 | |
| parent | 296388e81bd8557449a2027f8e8fa664307b5944 (diff) | |
| download | haskell-ac51be0997c4d0cf65cb3635b936ddf011e372bd.tar.gz | |
expand/fix comment about x86-64 registers
| -rw-r--r-- | compiler/nativeGen/X86/Regs.hs | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/compiler/nativeGen/X86/Regs.hs b/compiler/nativeGen/X86/Regs.hs index dc0df49874..28d148c12c 100644 --- a/compiler/nativeGen/X86/Regs.hs +++ b/compiler/nativeGen/X86/Regs.hs @@ -332,10 +332,24 @@ fake5 = regSingle 21 {- AMD x86_64 architecture: -- Registers 0-16 have 32-bit counterparts (eax, ebx etc.) -- Registers 0-7 have 16-bit counterparts (ax, bx etc.) -- Registers 0-3 have 8 bit counterparts (ah, bh etc.) - +- All 16 integer registers are addressable as 8, 16, 32 and 64-bit values: + + 8 16 32 64 + --------------------- + al ax eax rax + bl bx ebx rbx + cl cx ecx rcx + dl dx edx rdx + sil si esi rsi + dil si edi rdi + bpl bp ebp rbp + spl sp esp rsp + r10b r10w r10d r10 + r11b r11w r11d r11 + r12b r12w r12d r12 + r13b r13w r13d r13 + r14b r14w r14d r14 + r15b r15w r15d r15 -} rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi, |