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| author | Shea Levy <shea@shealevy.com> | 2018-02-25 20:34:39 -0500 |
|---|---|---|
| committer | Mark H Weaver <mhw@netris.org> | 2018-03-15 23:15:44 -0400 |
| commit | 08bb4628369cf3efe7c96a32919705c41a9ed9e9 (patch) | |
| tree | 4504cac1f3fb1c4e5d6d32c695cca24eb17042ec | |
| parent | 39860539599f74958c0cc9008fc6fa271349b58b (diff) | |
| download | guile-08bb4628369cf3efe7c96a32919705c41a9ed9e9.tar.gz | |
Recognize RISC-V compilation targets.
* module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.
Signed-off-by: Shea Levy <shea@shealevy.com>
Signed-off-by: Mark H Weaver <mhw@netris.org>
| -rw-r--r-- | module/system/base/target.scm | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/module/system/base/target.scm b/module/system/base/target.scm index e80bf84e4..8af199537 100644 --- a/module/system/base/target.scm +++ b/module/system/base/target.scm @@ -78,6 +78,8 @@ (endianness big)) ((string=? "aarch64" cpu) (endianness little)) + ((string-match "riscv[1-9][0-9]*" cpu) + (endianness little)) (else (error "unknown CPU endianness" cpu))))) |