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| author | chappedm@gmail.com <chappedm@gmail.com@6b5cf1ce-ec42-a296-1ba9-69fdba395a50> | 2013-03-11 00:23:03 +0000 |
|---|---|---|
| committer | chappedm@gmail.com <chappedm@gmail.com@6b5cf1ce-ec42-a296-1ba9-69fdba395a50> | 2013-03-11 00:23:03 +0000 |
| commit | beb78cc05babf0a49d21aed0ec789f19fc0f2d28 (patch) | |
| tree | 0a6c6a1a1e28a21ad34a014cdb01072eec9cf92d /src/base | |
| parent | bd3b3a7e9a67fac846cf574f5bfd241157bdfe3c (diff) | |
| download | gperftools-beb78cc05babf0a49d21aed0ec789f19fc0f2d28.tar.gz | |
issue-493: Fix for building against ARM targets
gperftools was failing to build for arm targets for the following reasons:
1. Some ARMv7 instructions used when the target is ARMv6 so those fail to assemble
2. The cache line length is undefined for ARM architectures
git-svn-id: http://gperftools.googlecode.com/svn/trunk@197 6b5cf1ce-ec42-a296-1ba9-69fdba395a50
Diffstat (limited to 'src/base')
| -rw-r--r-- | src/base/atomicops-internals-arm-v6plus.h | 5 | ||||
| -rw-r--r-- | src/base/basictypes.h | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/base/atomicops-internals-arm-v6plus.h b/src/base/atomicops-internals-arm-v6plus.h index e7cecf6..0aa6fdb 100644 --- a/src/base/atomicops-internals-arm-v6plus.h +++ b/src/base/atomicops-internals-arm-v6plus.h @@ -95,7 +95,12 @@ inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, } inline void MemoryBarrier() { +#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_6T2__) + uint32_t dest = 0; + __asm__ __volatile__("mcr p15,0,%0,c7,c10,5" :"=&r"(dest) : : "memory"); +#else __asm__ __volatile__("dmb" : : : "memory"); +#endif } inline Atomic32 Acquire_AtomicExchange(volatile Atomic32* ptr, diff --git a/src/base/basictypes.h b/src/base/basictypes.h index b002aa5..8b0518b 100644 --- a/src/base/basictypes.h +++ b/src/base/basictypes.h @@ -338,6 +338,11 @@ class AssignAttributeStartEnd { # define CACHELINE_ALIGNED __attribute__((aligned(32))) # elif (defined(__PPC__) || defined(__PPC64__)) # define CACHELINE_ALIGNED __attribute__((aligned(16))) +# elif (defined(__arm__)) +# define CACHELINE_ALIGNED __attribute__((aligned(64))) + // some ARMs have shorter cache lines (ARM1176JZF-S is 32 bytes for example) but obviously 64-byte aligned implies 32-byte aligned +# else +# error Could not determine cache line length - unknown architecture # endif #else # define CACHELINE_ALIGNED |