diff options
author | chappedm@gmail.com <chappedm@gmail.com@6b5cf1ce-ec42-a296-1ba9-69fdba395a50> | 2012-11-04 23:08:17 +0000 |
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committer | chappedm@gmail.com <chappedm@gmail.com@6b5cf1ce-ec42-a296-1ba9-69fdba395a50> | 2012-11-04 23:08:17 +0000 |
commit | 46f06ca0db41d3f598750caefdaf3c6063969e64 (patch) | |
tree | 3c4561be4ded1b114661811464afd17fc7264673 /src/base | |
parent | 5fe91d5623c2351ba4675db71822fc6be5e2cbce (diff) | |
download | gperftools-46f06ca0db41d3f598750caefdaf3c6063969e64.tar.gz |
issue-451: Fixed incorrect assembly for 64-bit barrier load and store on windows platforms.
git-svn-id: http://gperftools.googlecode.com/svn/trunk@181 6b5cf1ce-ec42-a296-1ba9-69fdba395a50
Diffstat (limited to 'src/base')
-rw-r--r-- | src/base/atomicops-internals-windows.h | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/src/base/atomicops-internals-windows.h b/src/base/atomicops-internals-windows.h index 5c1ae8c..ca16e39 100644 --- a/src/base/atomicops-internals-windows.h +++ b/src/base/atomicops-internals-windows.h @@ -434,12 +434,14 @@ inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, #endif } -inline void NoBarrier_Store(volatile Atomic64* ptrValue, Atomic64 value) { - __asm { - movq mm0, value; // Use mmx reg for 64-bit atomic moves - movq ptrValue, mm0; - emms; // Empty mmx state to enable FP registers - } +inline void NoBarrier_Store(volatile Atomic64* ptrValue, Atomic64 value) +{ + __asm { + movq mm0, value; // Use mmx reg for 64-bit atomic moves + mov eax, ptrValue; + movq [eax], mm0; + emms; // Empty mmx state to enable FP registers + } } inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) { @@ -451,14 +453,16 @@ inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) { NoBarrier_Store(ptr, value); } -inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptrValue) { - Atomic64 value; - __asm { - movq mm0, ptrValue; // Use mmx reg for 64-bit atomic moves - movq value, mm0; - emms; // Empty mmx state to enable FP registers - } - return value; +inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptrValue) +{ + Atomic64 value; + __asm { + mov eax, ptrValue; + movq mm0, [eax]; // Use mmx reg for 64-bit atomic moves + movq value, mm0; + emms; // Empty mmx state to enable FP registers + } + return value; } inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) { |