1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
|
/* From the Intel IA-64 Optimization Guide, choose the minimum latency
alternative. */
#include <sysdep.h>
#undef ret
#include <shlib-compat.h>
#if SHLIB_COMPAT(libc, GLIBC_2_2, GLIBC_2_2_6)
/* __divtf3
Compute a 80-bit IEEE double-extended quotient.
farg0 holds the dividend. farg1 holds the divisor. */
ENTRY(___divtf3)
cmp.eq p7, p0 = r0, r0
frcpa.s0 f10, p6 = farg0, farg1
;;
(p6) cmp.ne p7, p0 = r0, r0
.pred.rel.mutex p6, p7
(p6) fnma.s1 f11 = farg1, f10, f1
(p6) fma.s1 f12 = farg0, f10, f0
;;
(p6) fma.s1 f13 = f11, f11, f0
(p6) fma.s1 f14 = f11, f11, f11
;;
(p6) fma.s1 f11 = f13, f13, f11
(p6) fma.s1 f13 = f14, f10, f10
;;
(p6) fma.s1 f10 = f13, f11, f10
(p6) fnma.s1 f11 = farg1, f12, farg0
;;
(p6) fma.s1 f11 = f11, f10, f12
(p6) fnma.s1 f12 = farg1, f10, f1
;;
(p6) fma.s1 f10 = f12, f10, f10
(p6) fnma.s1 f12 = farg1, f11, farg0
;;
(p6) fma.s0 fret0 = f12, f10, f11
(p7) mov fret0 = f10
br.ret.sptk rp
END(___divtf3)
.symver ___divtf3, __divtf3@GLIBC_2.2
/* __divdf3
Compute a 64-bit IEEE double quotient.
farg0 holds the dividend. farg1 holds the divisor. */
ENTRY(___divdf3)
cmp.eq p7, p0 = r0, r0
frcpa.s0 f10, p6 = farg0, farg1
;;
(p6) cmp.ne p7, p0 = r0, r0
.pred.rel.mutex p6, p7
(p6) fmpy.s1 f11 = farg0, f10
(p6) fnma.s1 f12 = farg1, f10, f1
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fmpy.s1 f13 = f12, f12
;;
(p6) fma.s1 f10 = f12, f10, f10
(p6) fma.s1 f11 = f13, f11, f11
;;
(p6) fmpy.s1 f12 = f13, f13
(p6) fma.s1 f10 = f13, f10, f10
;;
(p6) fma.d.s1 f11 = f12, f11, f11
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fnma.d.s1 f8 = farg1, f11, farg0
;;
(p6) fma.d fret0 = f8, f10, f11
(p7) mov fret0 = f10
br.ret.sptk rp
;;
END(___divdf3)
.symver ___divdf3, __divdf3@GLIBC_2.2
/* __divsf3
Compute a 32-bit IEEE float quotient.
farg0 holds the dividend. farg1 holds the divisor. */
ENTRY(___divsf3)
cmp.eq p7, p0 = r0, r0
frcpa.s0 f10, p6 = farg0, farg1
;;
(p6) cmp.ne p7, p0 = r0, r0
.pred.rel.mutex p6, p7
(p6) fmpy.s1 f8 = farg0, f10
(p6) fnma.s1 f9 = farg1, f10, f1
;;
(p6) fma.s1 f8 = f9, f8, f8
(p6) fmpy.s1 f9 = f9, f9
;;
(p6) fma.s1 f8 = f9, f8, f8
(p6) fmpy.s1 f9 = f9, f9
;;
(p6) fma.d.s1 f10 = f9, f8, f8
;;
(p6) fnorm.s.s0 fret0 = f10
(p7) mov fret0 = f10
br.ret.sptk rp
;;
END(___divsf3)
.symver ___divsf3, __divsf3@GLIBC_2.2
/* __divdi3
Compute a 64-bit integer quotient.
in0 holds the dividend. in1 holds the divisor. */
ENTRY(___divdi3)
.regstk 2,0,0,0
/* Transfer inputs to FP registers. */
setf.sig f8 = in0
setf.sig f9 = in1
;;
/* Convert the inputs to FP, so that they won't be treated as
unsigned. */
fcvt.xf f8 = f8
fcvt.xf f9 = f9
;;
/* Compute the reciprocal approximation. */
frcpa.s1 f10, p6 = f8, f9
;;
/* 3 Newton-Raphson iterations. */
(p6) fnma.s1 f11 = f9, f10, f1
(p6) fmpy.s1 f12 = f8, f10
;;
(p6) fmpy.s1 f13 = f11, f11
(p6) fma.s1 f12 = f11, f12, f12
;;
(p6) fma.s1 f10 = f11, f10, f10
(p6) fma.s1 f11 = f13, f12, f12
;;
(p6) fma.s1 f10 = f13, f10, f10
(p6) fnma.s1 f12 = f9, f11, f8
;;
(p6) fma.s1 f10 = f12, f10, f11
;;
/* Round quotient to an integer. */
fcvt.fx.trunc.s1 f10 = f10
;;
/* Transfer result to GP registers. */
getf.sig ret0 = f10
br.ret.sptk rp
;;
END(___divdi3)
.symver ___divdi3, __divdi3@GLIBC_2.2
/* __moddi3
Compute a 64-bit integer modulus.
in0 holds the dividend (a). in1 holds the divisor (b). */
ENTRY(___moddi3)
.regstk 2,0,0,0
/* Transfer inputs to FP registers. */
setf.sig f14 = in0
setf.sig f9 = in1
;;
/* Convert the inputs to FP, so that they won't be treated as
unsigned. */
fcvt.xf f8 = f14
fcvt.xf f9 = f9
;;
/* Compute the reciprocal approximation. */
frcpa.s1 f10, p6 = f8, f9
;;
/* 3 Newton-Raphson iterations. */
(p6) fmpy.s1 f12 = f8, f10
(p6) fnma.s1 f11 = f9, f10, f1
;;
(p6) fma.s1 f12 = f11, f12, f12
(p6) fmpy.s1 f13 = f11, f11
;;
(p6) fma.s1 f10 = f11, f10, f10
(p6) fma.s1 f11 = f13, f12, f12
;;
sub in1 = r0, in1
(p6) fma.s1 f10 = f13, f10, f10
(p6) fnma.s1 f12 = f9, f11, f8
;;
setf.sig f9 = in1
(p6) fma.s1 f10 = f12, f10, f11
;;
fcvt.fx.trunc.s1 f10 = f10
;;
/* r = q * (-b) + a */
xma.l f10 = f10, f9, f14
;;
/* Transfer result to GP registers. */
getf.sig ret0 = f10
br.ret.sptk rp
;;
END(___moddi3)
.symver ___moddi3, __moddi3@GLIBC_2.2
/* __udivdi3
Compute a 64-bit unsigned integer quotient.
in0 holds the dividend. in1 holds the divisor. */
ENTRY(___udivdi3)
.regstk 2,0,0,0
/* Transfer inputs to FP registers. */
setf.sig f8 = in0
setf.sig f9 = in1
;;
/* Convert the inputs to FP, to avoid FP software-assist faults. */
fcvt.xuf.s1 f8 = f8
fcvt.xuf.s1 f9 = f9
;;
/* Compute the reciprocal approximation. */
frcpa.s1 f10, p6 = f8, f9
;;
/* 3 Newton-Raphson iterations. */
(p6) fnma.s1 f11 = f9, f10, f1
(p6) fmpy.s1 f12 = f8, f10
;;
(p6) fmpy.s1 f13 = f11, f11
(p6) fma.s1 f12 = f11, f12, f12
;;
(p6) fma.s1 f10 = f11, f10, f10
(p6) fma.s1 f11 = f13, f12, f12
;;
(p6) fma.s1 f10 = f13, f10, f10
(p6) fnma.s1 f12 = f9, f11, f8
;;
(p6) fma.s1 f10 = f12, f10, f11
;;
/* Round quotient to an unsigned integer. */
fcvt.fxu.trunc.s1 f10 = f10
;;
/* Transfer result to GP registers. */
getf.sig ret0 = f10
br.ret.sptk rp
;;
END(___udivdi3)
.symver ___udivdi3, __udivdi3@GLIBC_2.2
/* __umoddi3
Compute a 64-bit unsigned integer modulus.
in0 holds the dividend (a). in1 holds the divisor (b). */
ENTRY(___umoddi3)
.regstk 2,0,0,0
/* Transfer inputs to FP registers. */
setf.sig f14 = in0
setf.sig f9 = in1
;;
/* Convert the inputs to FP, to avoid FP software assist faults. */
fcvt.xuf.s1 f8 = f14
fcvt.xuf.s1 f9 = f9
;;
/* Compute the reciprocal approximation. */
frcpa.s1 f10, p6 = f8, f9
;;
/* 3 Newton-Raphson iterations. */
(p6) fmpy.s1 f12 = f8, f10
(p6) fnma.s1 f11 = f9, f10, f1
;;
(p6) fma.s1 f12 = f11, f12, f12
(p6) fmpy.s1 f13 = f11, f11
;;
(p6) fma.s1 f10 = f11, f10, f10
(p6) fma.s1 f11 = f13, f12, f12
;;
sub in1 = r0, in1
(p6) fma.s1 f10 = f13, f10, f10
(p6) fnma.s1 f12 = f9, f11, f8
;;
setf.sig f9 = in1
(p6) fma.s1 f10 = f12, f10, f11
;;
/* Round quotient to an unsigned integer. */
fcvt.fxu.trunc.s1 f10 = f10
;;
/* r = q * (-b) + a */
xma.l f10 = f10, f9, f14
;;
/* Transfer result to GP registers. */
getf.sig ret0 = f10
br.ret.sptk rp
;;
END(___umoddi3)
.symver ___umoddi3, __umoddi3@GLIBC_2.2
/* __multi3
Compute a 128-bit multiply of 128-bit multiplicands.
in0/in1 holds one multiplicand (a), in2/in3 holds the other one (b). */
ENTRY(___multi3)
.regstk 4,0,0,0
setf.sig f6 = in1
movl r19 = 0xffffffff
setf.sig f7 = in2
;;
and r14 = r19, in0
;;
setf.sig f10 = r14
and r14 = r19, in2
xmpy.l f9 = f6, f7
;;
setf.sig f6 = r14
shr.u r14 = in0, 32
;;
setf.sig f7 = r14
shr.u r14 = in2, 32
;;
setf.sig f8 = r14
xmpy.l f11 = f10, f6
xmpy.l f6 = f7, f6
;;
getf.sig r16 = f11
xmpy.l f7 = f7, f8
;;
shr.u r14 = r16, 32
and r16 = r19, r16
getf.sig r17 = f6
setf.sig f6 = in0
;;
setf.sig f11 = r14
getf.sig r21 = f7
setf.sig f7 = in3
;;
xma.l f11 = f10, f8, f11
xma.l f6 = f6, f7, f9
;;
getf.sig r18 = f11
;;
add r18 = r18, r17
;;
and r15 = r19, r18
cmp.ltu p7, p6 = r18, r17
;;
getf.sig r22 = f6
(p7) adds r14 = 1, r19
;;
(p7) add r21 = r21, r14
shr.u r14 = r18, 32
shl r15 = r15, 32
;;
add r20 = r21, r14
;;
add ret0 = r15, r16
add ret1 = r22, r20
br.ret.sptk rp
;;
END(___multi3)
.symver ___multi3, __multi3@GLIBC_2.2
#endif
|
