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* posix_spawn: fix stack setup on ia64 [BZ #21275]gentoo/2.24Mike Frysinger2017-03-201-5/+6
| | | | | | | | | | | The ia64-specific clone2 call expects the base of the stack mapping and the stack size as sep arguments, not an initial stack value as on other stack-grows-down architectures. Reuse the stack-grows-up macro so we pass in the right stack base. Reported-by: Matt Turner <mattst88@gentoo.org> (cherry picked from commit ddc3fb333469c2997798742dc0509dc1e3201d91) (cherry picked from commit 7043946c7921c0e3850dd2b3d948336624bb0f62)
* Revert "sys/types.h: drop sys/sysmacros.h include"Mike Frysinger2017-02-091-0/+3
| | | | | | | This reverts commit 92bf87d8c4837feaec62958be59c3119b8b4f5ae. We keep this in the testing version, but once we want to start stabilizing, we drop it.
* X86_64: Don't use PLT nor GOT in static archives [BZ #20750]H.J. Lu2017-02-091-1/+2
| | | | | | | | | | | | | | There is no need to use PLT nor GOT in static archives to branch to a function, regardless whether static archives is compiled with PIC or not. When static archives are used to create dynamic executable, PLT/GOT may be used. The resulting executable still works correctly. [BZ #20750] * sysdeps/x86_64/sysdep.h (JUMPTARGET): Check SHARED instead of PIC. (cherry picked from commit c9070e6305c08365c5f8b604bdca39c699d70cfa) (cherry picked from commit d012ea850680a2a94959f1c5136502a0f712b30a)
* CVE-2015-5180: resolv: Fix crash with internal QTYPE [BZ #18784]Florian Weimer2017-02-096-7/+201
| | | | | | | | Also rename T_UNSPEC because an upcoming public header file update will use that name. (cherry picked from commit fc82b0a2dfe7dbd35671c10510a8da1043d746a5) (cherry picked from commit b3b37f1a5559a7620e31c8053ed1b44f798f2b6d)
* Drop GLIBC_TUNABLES in setxid processesSiddhesh Poyarekar2017-02-091-0/+1
| | | | | | | | | | | | Drop the GLIBC_TUNABLES environment variable from the environment of setxid processes to avoid passing it on to non-setxid children. This prevents potentially insecure tunables in the GLIBC_TUNABLES envvar from crossing over into a child that may use a libc that has tunables support. * sysdeps/generic/unsecvars.h: Add GLIBC_TUNABLES. (cherry picked from commit 537a06fbdeb9a6c2184c745c15ef3346681f5eeb)
* powerpc: Fix write-after-destroy in lock elision [BZ #20822]Tulio Magno Quites Machado Filho2017-02-093-12/+20
| | | | | | | | | | | The update of *adapt_count after the release of the lock causes a race condition when thread A unlocks, thread B continues and destroys the mutex, and thread A writes to *adapt_count. (cherry picked from commit e9a96ea1aca4ebaa7c86e8b83b766f118d689d0f) (with changes from commit eb1321f291515dae75c83a40c39e775fdd38e97a) (cherry picked from commit 2762a7145bba9681b30ed5d4aed0c5d1df4329c8)
* localedata: bs_BA: fix yesexpr/noexpr [BZ #20974]Mike Frysinger2016-12-301-2/+2
| | | | | | | | | | | | Both regexes end with a "*." which means the previous match can be omitted, and then the . allows them to match any input at all. This means tools like coreutils' `rm -i` will always delete things when prompted because the yesexpr regex matches all inputs (even the negative ones). (cherry picked from commit a035eb6928bc63fb798dcc1421529f933122d74f) (cherry picked from commit 7e4405c50fc374d5e80141554c7887a52d1f9118)
* Bug 11941: ld.so: Improper assert map->l_init_called in dlcloseCarlos O'Donell2016-12-305-8/+203
| | | | | | | | | | | | | | | | There is at least one use case where during exit a library destructor might call dlclose() on a valid handle and have it fail with an assertion. We must allow this case, it is a valid handle, and dlclose() should not fail with an assert. In the future we might be able to return an error that the dlclose() could not be completed because the opened library has already been unloaded and destructors have run as part of exit processing. For more details see: https://www.sourceware.org/ml/libc-alpha/2016-12/msg00859.html (cherry picked from commit 57707b7fcc38855869321f8c7827bfe21d729f37) (cherry picked from commit e9e69e468039fcd57276f783a16aa771a8e4214e)
* alpha: fix trunc for big input valuesAurelien Jarno2016-12-082-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The alpha specific version of trunc and truncf always add and subtract 0x1.0p23 or 0x1.0p52 even for big values. This causes this kind of errors in the testsuite: Failure: Test: trunc_towardzero (0x1p107) Result: is: 1.6225927682921334e+32 0x1.fffffffffffffp+106 should be: 1.6225927682921336e+32 0x1.0000000000000p+107 difference: 1.8014398509481984e+16 0x1.0000000000000p+54 ulp : 0.5000 max.ulp : 0.0000 Change this by returning the input value when its absolute value is greater than 0x1.0p23 or 0x1.0p52. NaN have to go through the add and subtract operations to get possibly silenced. Finally remove the code to handle inexact exception, trunc should never generate such an exception. Changelog: * sysdeps/alpha/fpu/s_trunc.c (__trunc): Return the input value when its absolute value is greater than 0x1.0p52. [_IEEE_FP_INEXACT] Remove. * sysdeps/alpha/fpu/s_truncf.c (__truncf): Return the input value when its absolute value is greater than 0x1.0p23. [_IEEE_FP_INEXACT] Remove. (cherry picked from commit b74d259fe793499134eb743222cd8dd7c74a31ce) (cherry picked from commit e6eab16cc302e6c42f79e1af02ce98ebb9a783bc)
* alpha: fix rint on sNaN inputAurelien Jarno2016-12-082-0/+6
| | | | | | | | | | | | | | The alpha version of rint wrongly return sNaN for sNaN input. Fix that by checking for NaN and by returning the input value added with itself in that case. Changelog: * sysdeps/alpha/fpu/s_rint.c (__rint): Add argument with itself when it is a NaN. * sysdeps/alpha/fpu/s_rintf.c (__rintf): Likewise. (cherry picked from commit cb7f9d63b921ea1a1cbb4ab377a8484fd5da9a2b) (cherry picked from commit 8eb9a92e0522f2d4f2d4167df919d066c85d3408)
* alpha: fix floor on sNaN inputAurelien Jarno2016-12-082-8/+6
| | | | | | | | | | | | | | | | | | The alpha version of floor wrongly return sNaN for sNaN input. Fix that by checking for NaN and by returning the input value added with itself in that case. Finally remove the code to handle inexact exception, floor should never generate such an exception. Changelog: * sysdeps/alpha/fpu/s_floor.c (__floor): Add argument with itself when it is a NaN. [_IEEE_FP_INEXACT] Remove. * sysdeps/alpha/fpu/s_floorf.c (__floorf): Likewise. (cherry picked from commit 65cc568cf57156e5230db9a061645e54ff028a41) (cherry picked from commit 1912cc082df4739c2388c375f8d486afdaa7d49b)
* alpha: fix ceil on sNaN inputAurelien Jarno2016-12-082-8/+6
| | | | | | | | | | | | | | | | | | The alpha version of ceil wrongly return sNaN for sNaN input. Fix that by checking for NaN and by returning the input value added with itself in that case. Finally remove the code to handle inexact exception, ceil should never generate such an exception. Changelog: * sysdeps/alpha/fpu/s_ceil.c (__ceil): Add argument with itself when it is a NaN. [_IEEE_FP_INEXACT] Remove. * sysdeps/alpha/fpu/s_ceilf.c (__ceilf): Likewise. (cherry picked from commit 062e53c195b4a87754632c7d51254867247698b4) (cherry picked from commit 3eff6f84311d2679a58a637e3be78b4ced275762)
* X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]H.J. Lu2016-12-081-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is transition penalty when SSE instructions are mixed with 256-bit AVX or 512-bit AVX512 load instructions. Since _dl_runtime_resolve_avx and _dl_runtime_profile_avx512 save/restore 256-bit YMM/512-bit ZMM registers, there is transition penalty when SSE instructions are used with lazy binding on AVX and AVX512 processors. To avoid SSE transition penalty, if only the lower 128 bits of the first 8 vector registers are non-zero, we can preserve %xmm0 - %xmm7 registers with the zero upper bits. For AVX and AVX512 processors which support XGETBV with ECX == 1, we can use XGETBV with ECX == 1 to check if the upper 128 bits of YMM registers or the upper 256 bits of ZMM registers are zero. We can restore only the non-zero portion of vector registers with AVX/AVX512 load instructions which will zero-extend upper bits of vector registers. This patch adds _dl_runtime_resolve_sse_vex which saves and restores XMM registers with 128-bit AVX store/load instructions. It is used to preserve YMM/ZMM registers when only the lower 128 bits are non-zero. _dl_runtime_resolve_avx_opt and _dl_runtime_resolve_avx512_opt are added and used on AVX/AVX512 processors supporting XGETBV with ECX == 1 so that we store and load only the non-zero portion of vector registers. This avoids SSE transition penalty caused by _dl_runtime_resolve_avx and _dl_runtime_profile_avx512 when only the lower 128 bits of vector registers are used. _dl_runtime_resolve_avx_slow is added and used for AVX processors which don't support XGETBV with ECX == 1. Since there is no SSE transition penalty on AVX512 processors which don't support XGETBV with ECX == 1, _dl_runtime_resolve_avx512_slow isn't provided. [BZ #20495] [BZ #20508] * sysdeps/x86/cpu-features.c (init_cpu_features): For Intel processors, set Use_dl_runtime_resolve_slow and set Use_dl_runtime_resolve_opt if XGETBV suports ECX == 1. * sysdeps/x86/cpu-features.h (bit_arch_Use_dl_runtime_resolve_opt): New. (bit_arch_Use_dl_runtime_resolve_slow): Likewise. (index_arch_Use_dl_runtime_resolve_opt): Likewise. (index_arch_Use_dl_runtime_resolve_slow): Likewise. * sysdeps/x86_64/dl-machine.h (elf_machine_runtime_setup): Use _dl_runtime_resolve_avx512_opt and _dl_runtime_resolve_avx_opt if Use_dl_runtime_resolve_opt is set. Use _dl_runtime_resolve_slow if Use_dl_runtime_resolve_slow is set. * sysdeps/x86_64/dl-trampoline.S: Include <cpu-features.h>. (_dl_runtime_resolve_opt): New. Defined for AVX and AVX512. (_dl_runtime_resolve): Add one for _dl_runtime_resolve_sse_vex. * sysdeps/x86_64/dl-trampoline.h (_dl_runtime_resolve_avx_slow): New. (_dl_runtime_resolve_opt): Likewise. (_dl_runtime_profile): Define only if _dl_runtime_profile is defined. (cherry picked from commit fb0f7a6755c1bfaec38f490fbfcaa39a66ee3604)
* X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]H.J. Lu2016-12-085-3/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is transition penalty when SSE instructions are mixed with 256-bit AVX or 512-bit AVX512 load instructions. Since _dl_runtime_resolve_avx and _dl_runtime_profile_avx512 save/restore 256-bit YMM/512-bit ZMM registers, there is transition penalty when SSE instructions are used with lazy binding on AVX and AVX512 processors. To avoid SSE transition penalty, if only the lower 128 bits of the first 8 vector registers are non-zero, we can preserve %xmm0 - %xmm7 registers with the zero upper bits. For AVX and AVX512 processors which support XGETBV with ECX == 1, we can use XGETBV with ECX == 1 to check if the upper 128 bits of YMM registers or the upper 256 bits of ZMM registers are zero. We can restore only the non-zero portion of vector registers with AVX/AVX512 load instructions which will zero-extend upper bits of vector registers. This patch adds _dl_runtime_resolve_sse_vex which saves and restores XMM registers with 128-bit AVX store/load instructions. It is used to preserve YMM/ZMM registers when only the lower 128 bits are non-zero. _dl_runtime_resolve_avx_opt and _dl_runtime_resolve_avx512_opt are added and used on AVX/AVX512 processors supporting XGETBV with ECX == 1 so that we store and load only the non-zero portion of vector registers. This avoids SSE transition penalty caused by _dl_runtime_resolve_avx and _dl_runtime_profile_avx512 when only the lower 128 bits of vector registers are used. _dl_runtime_resolve_avx_slow is added and used for AVX processors which don't support XGETBV with ECX == 1. Since there is no SSE transition penalty on AVX512 processors which don't support XGETBV with ECX == 1, _dl_runtime_resolve_avx512_slow isn't provided. [BZ #20495] [BZ #20508] * sysdeps/x86/cpu-features.c (init_cpu_features): For Intel processors, set Use_dl_runtime_resolve_slow and set Use_dl_runtime_resolve_opt if XGETBV suports ECX == 1. * sysdeps/x86/cpu-features.h (bit_arch_Use_dl_runtime_resolve_opt): New. (bit_arch_Use_dl_runtime_resolve_slow): Likewise. (index_arch_Use_dl_runtime_resolve_opt): Likewise. (index_arch_Use_dl_runtime_resolve_slow): Likewise. * sysdeps/x86_64/dl-machine.h (elf_machine_runtime_setup): Use _dl_runtime_resolve_avx512_opt and _dl_runtime_resolve_avx_opt if Use_dl_runtime_resolve_opt is set. Use _dl_runtime_resolve_slow if Use_dl_runtime_resolve_slow is set. * sysdeps/x86_64/dl-trampoline.S: Include <cpu-features.h>. (_dl_runtime_resolve_opt): New. Defined for AVX and AVX512. (_dl_runtime_resolve): Add one for _dl_runtime_resolve_sse_vex. * sysdeps/x86_64/dl-trampoline.h (_dl_runtime_resolve_avx_slow): New. (_dl_runtime_resolve_opt): Likewise. (_dl_runtime_profile): Define only if _dl_runtime_profile is defined. (cherry picked from commit fb0f7a6755c1bfaec38f490fbfcaa39a66ee3604) (cherry picked from commit 4b8790c81c1a7b870a43810ec95e08a2e501123d)
* x86_64: fix static build of __memcpy_chk for compilers defaulting to PIC/PIEAurelien Jarno2016-12-081-1/+1
| | | | | | | | | | | | | | When glibc is compiled with gcc 6.2 that has been configured with to default to PIC/PIE, the static version of __memcpy_chk is not built, as the test is done on PIC instead of SHARED. Fix the test to check for SHARED, like it is done for similar functions like memmove_chk. Changelog: * sysdeps/x86_64/memcpy_chk.S (__memcpy_chk): Check for SHARED instead of PIC. (cherry picked from commit 380ec16d62f459d5a28cfc25b7b20990c45e1cc9) (cherry picked from commit 2d16e81babd1d7b66d10cec0bc6d6d86a7e0c95e)
* MIPS: Add `.insn' to ensure a text label is defined as code not dataMaciej W. Rozycki2016-12-083-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid a build error with microMIPS compilation and recent versions of GAS which complain if a branch targets a label which is marked as data rather than microMIPS code: ../sysdeps/mips/mips32/crti.S: Assembler messages: ../sysdeps/mips/mips32/crti.S:72: Error: branch to a symbol in another ISA mode make[2]: *** [.../csu/crti.o] Error 1 as commit 9d862524f6ae ("MIPS: Verify the ISA mode and alignment of branch and jump targets") closed a hole in branch processing, making relocation calculation respect the ISA mode of the symbol referred. This allowed diagnosing the situation where an attempt is made to pass control from code assembled for one ISA mode to code assembled for a different ISA mode and either relaxing the branch to a cross-mode jump or if that is not possible, then reporting this as an error rather than letting such code build and then fail unpredictably at the run time. This however requires the correct annotation of branch targets as code, because the ISA mode is not relevant for data symbols and is therefore not recorded for them. The `.insn' pseudo-op is used for this purpose and has been supported by GAS since: Wed Feb 12 14:36:29 1997 Ian Lance Taylor <ian@cygnus.com> * config/tc-mips.c (mips_pseudo_table): Add "insn". (s_insn): New static function. * doc/c-mips.texi: Document .insn. so there has been no reason to avoid it where required. More recently this pseudo-op has been documented, by the microMIPS architecture specification[1][2], as required for the correct interpretation of any code label which is not followed by an actual instruction in an assembly source. Use it in our crti.S files then, to mark that the trailing label there with no instructions following is indeed not a code bug and the branch is legitimate. References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level Compatibility", p. 533 [2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level Compatibility", p. 623 2016-11-23 Matthew Fortune <Matthew.Fortune@imgtec.com> Maciej W. Rozycki <macro@imgtec.com> * sysdeps/mips/mips32/crti.S (_init): Add `.insn' pseudo-op at `.Lno_weak_fn' label. * sysdeps/mips/mips64/n32/crti.S (_init): Likewise. * sysdeps/mips/mips64/n64/crti.S (_init): Likewise. (cherry picked from commit cfaf1949ff1f8336b54c43796d0e2531bc8a40a2) (cherry picked from commit 65a2b63756a4d622b938910d582d8b807c471c9a)
* Fix writes past the allocated array bounds in execvpe (BZ#20847)Adhemerval Zanella2016-12-081-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an invalid write out or stack allocated buffer in 2 places at execvpe implementation: 1. On 'maybe_script_execute' function where it allocates the new argument list and it does not account that a minimum of argc plus 3 elements (default shell path, script name, arguments, and ending null pointer) should be considered. The straightforward fix is just to take account of the correct list size on argument copy. 2. On '__execvpe' where the executable file name lenght may not account for ending '\0' and thus subsequent path creation may write past array bounds because it requires to add the terminating null. The fix is to change how to calculate the executable name size to add the final '\0' and adjust the rest of the code accordingly. As described in GCC bug report 78433 [1], these issues were masked off by GCC because it allocated several bytes more than necessary so that many off-by-one bugs went unnoticed. Checked on x86_64 with a latest GCC (7.0.0 20161121) with -O3 on CFLAGS. [BZ #20847] * posix/execvpe.c (maybe_script_execute): Remove write past allocated array bounds. (__execvpe): Likewise. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78433 (cherry picked from commit d174436712e3cabce70d6cd771f177b6fe0e097b)
* configure: accept __stack_chk_fail_local for ssp support too [BZ #20662]Denis Kaganovich2016-11-152-6/+10
| | | | | | | | | | | | | | | | | When glibc is compiled with gcc 6.2 that has been configured with --enable-default-pie and --enable-default-ssp, the configure script fails to detect that the compiler has ssp turned on by default when being built for i686-linux-gnu. This is because gcc is emitting __stack_chk_fail_local but the script is only looking for __stack_chk_fail. Support both. Example output: checking whether x86_64-pc-linux-gnu-gcc -m32 -Wl,-O1 -Wl,--as-needed implicitly enables -fstack-protector... no (cherry picked from commit c7409aded44634411a19b0b7178b7faa237835e6) (cherry picked from commit 2bdb3d2ee19a6ac61da0a398b10db380e9c92959)
* sys/types.h: drop sys/sysmacros.h includeMike Frysinger2016-11-111-3/+0
| | | | | We want to break apart this include path due to namespace pollution. https://sourceware.org/ml/libc-alpha/2015-11/msg00253.html
* gentoo: support running tests under sandboxStephanie J. Lockwood-Childs2016-11-113-3/+3
| | | | | | | | | | | | | | | | | when glibc runs its tests, it does so by invoking the local library loader. in Gentoo, we build/run inside of our "sandbox" which itself is linked against libdl (so that it can load libraries and pull out symbols). the trouble is that when you upgrade from an older glibc to the new one, often times internal symbols change name or abi. this is normally OK as you cannot use libc.so from say version 2.3.6 but libpthread.so from say version 2.5, so we always say "keep all of the glibc libraries from the same build". but when glibc runs its tests, it uses dynamic paths to point to its new local copies of libraries. if the test doesnt use libdl, then glibc doesnt add its path, and when sandbox triggers the loading of libdl, glibc does so from the host system system. this gets us into the case of all libraries are from the locally compiled version of glibc except for libdl.so. http://bugs.gentoo.org/56898
* rtld: do not ignore arch-specific CFLAGSCarlos O'Donell2016-11-111-1/+1
| | | | | | https://bugs.gentoo.org/452184 http://sourceware.org/bugzilla/show_bug.cgi?id=15005 http://sourceware.org/ml/libc-alpha/2013-01/msg00247.html
* reload /etc/resolv.conf when it has changedThorsten Kukuk2016-11-111-0/+15
| | | | | | | | | if /etc/resolv.conf is updated, then make sure applications already running get the updated information. ripped from SuSE http://bugs.gentoo.org/177416
* disable ldconfig during installMike Frysinger2016-11-111-0/+1
| | | | | | | | | | Do not bother running ldconfig on DESTDIR. It's a waste of time as we won't use the result (portage will rebuild the cache after install). Also, the Gentoo sandbox does not currently catch chroot() behavior so we end up (incorrectly) flagging it as a violation as a write to /etc. http://sourceware.org/ml/libc-alpha/2012-08/msg00118.html https://bugs.gentoo.org/431038
* Fix linknamespace parallel test failures.Joseph Myers2016-11-062-0/+6
| | | | | | | | | | | | | | | | Having found that with my script to build many glibc variants I could reproduce the linknamespace test failures in parallel builds (that various people had previously reported but I hadn't seen myself), I investigated those failures further. This patch adds a missing dependency to those tests. Tested for x86_64, including the configuration where I saw those failures and where I don't see them with this patch. * conform/Makefile ($(linknamespace-header-tests)): Also depend on $(linknamespace-symlists-tests). (cherry picked from commit 6c50bb532bb1f47084762e16fbf52af9b5a752d8)
* gconv.h: fix build with GCC 7Aurelien Jarno2016-11-062-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gconv.h is using a flex array to define the __gconv_info member in an invalid way, causing GCC 7 to issue an error: | In file included from ../include/gconv.h:1:0, | from ../sysdeps/unix/sysv/linux/_G_config.h:32, | from ../libio/libio.h:31, | from ../include/libio.h:4, | from ../libio/stdio.h:74, | from ../include/stdio.h:5, | from test-math-isinff.cc:22: | ../iconv/gconv.h:142:50: error: flexible array member '__gconv_info::__data' not at end of 'struct _IO_codecvt' | In file included from ../include/libio.h:4:0, | from ../libio/stdio.h:74, | from ../include/stdio.h:5, | from test-math-isinff.cc:22: | ../libio/libio.h:211:14: note: next member '_G_iconv_t _IO_codecvt::__cd_out' declared here | ../libio/libio.h:187:8: note: in the definition of 'struct _IO_codecvt' | In file included from ../include/gconv.h:1:0, | from ../sysdeps/unix/sysv/linux/_G_config.h:32, | from ../libio/libio.h:31, | from ../include/libio.h:4, | from ../libio/stdio.h:74, | from ../include/stdio.h:5, | from test-math-isinff.cc:22: | ../iconv/gconv.h:142:50: error: flexible array member '__gconv_info::__data' not at end of 'struct _IO_wide_data' | In file included from ../include/libio.h:4:0, | from ../libio/stdio.h:74, | from ../include/stdio.h:5, | from test-math-isinff.cc:22: | ../libio/libio.h:211:14: note: next member '_G_iconv_t _IO_codecvt::__cd_out' declared here | ../libio/libio.h:215:8: note: in the definition of 'struct _IO_wide_data' This is basically a revert to the code from 15 years ago. More details are available in the GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78039 Changelog: * iconv/gconv.h (__gconv_info): Define __data element using a zero-length array. (cherry picked from commit 0623b9e6a9c3441427cf8c421bcc81d09e48fdc1)
* Fix cmpli usage in power6 memset.Joseph Myers2016-11-063-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Building glibc for powerpc64 with recent (2.27.51.20161012) binutils, with multi-arch enabled, I get the error: ../sysdeps/powerpc/powerpc64/power6/memset.S: Assembler messages: ../sysdeps/powerpc/powerpc64/power6/memset.S:254: Error: operand out of range (5 is not between 0 and 1) ../sysdeps/powerpc/powerpc64/power6/memset.S:254: Error: operand out of range (128 is not between 0 and 31) ../sysdeps/powerpc/powerpc64/power6/memset.S:254: Error: missing operand Indeed, cmpli is documented as a four-operand instruction, and looking at nearby code it seems likely cmpldi was intended. This patch fixes this powerpc64 code accordingly, and makes a corresponding change to the powerpc32 code. Tested for powerpc, powerpc64 and powerpc64le by Tulio Magno Quites Machado Filho * sysdeps/powerpc/powerpc32/power6/memset.S (memset): Use cmplwi instead of cmpli. * sysdeps/powerpc/powerpc64/power6/memset.S (memset): Use cmpldi instead of cmpli. (cherry picked from commit 78b7adbaea643f2f213bb113e3ec933416a769a8)
* Fix Linux sh4 pread/pwrite argument passingAdhemerval Zanella2016-10-2411-100/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although conceptually correct for p{read,write}{64} offset argument passing, sh4 implementation does not generate the correct expected code. The __ALIGNMENT_ARG redefinition is incorrect for two reasons: 1. the kernel-features.h header is included multiple times (since it contains no guards) and 2. the value it redefines is also incorrect (should be '0, ' instead of empty definition). This patch fixes it by adding another macro, SYSCALL_LL_PRW{64}, meant to be used to pass the offset argument on p{read,write}64. It is basically the already define SYSCALL_LL{64} plus __ALIGNMENT_ARG unless __ASSUME_PRW_DUMMY_ARG is define. In this case an empty dummy argument is used regardless how __ALIGNMENT_ARG is defined (sh4 case). Checked on x86_64, i686, aarch64, armhf, and powerpc64le (basically a sanity check). Also, John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> and James Clarke <jrtc27@jrtc27.com> help me check on a debian sh4 bootstrap using 2.24 plus this patch to verify it also corrected fixed the regression issue. I also verified the generated object for a 2.24 build and master with this patch for sh4 and both look identical. * sysdeps/unix/sysv/linux/pread.c (__libc_pread): Use SYSCALL_LL_PRW. * sysdeps/unix/sysv/linux/pwrite.c (__libc_pwrite): Likewise. * sysdeps/unix/sysv/linux/pread64.c (__libc_pread64): Use SYSCALL_LL64_PRW. * sysdeps/unix/sysv/linux/pwrite64.c (__libc_pwrite64): Likewise. * sysdeps/unix/sysv/linux/sh/kernel-features.h: Define __ASSUME_PRW_DUMMY_ARG. * sysdeps/unix/sysv/linux/sh/pread.c: Remove file. * sysdeps/unix/sysv/linux/sh/pread64.c: Likewise. * sysdeps/unix/sysv/linux/sh/pwrite.c: Likewise. * sysdeps/unix/sysv/linux/sh/pwrite64.c: Likewise. * sysdeps/unix/sysv/linux/sysdep.h: Define SYSCALL_LL_PRW and SYSCALL_LL_PRW64 based on __ASSUME_PRW_DUMMY_ARG.
* powerpc: Regenerate ULPsTulio Magno Quites Machado Filho2016-10-052-53/+57
| | | | * sysdeps/powerpc/fpu/libm-test-ulps: Regenerated.
* posix: Correctly block/unblock all signals on Linux posix_spawnAdhemerval Zanella2016-09-282-6/+6
| | | | | | | | | | | | | This patch correctly block and unblocks all signals when executing Linux posix_spawn by using the __libc_signal_{un}block_all functions instead of default sigprocmask. The latter might remove both SIGCANCEL and SIGSETXID from the blocked signal list. Checked on x86_64, i686, powerpc64le, and aarch64. * sysdeps/unix/sysv/linux/spawni.c (__spawnix): Correctly block and unblock all signals when executing the clone vfork child. (SIGALL_SET): Remove macro.
* posix: Correctly enable/disable cancellation on Linux posix_spawnAdhemerval Zanella2016-09-284-3/+208
| | | | | | | | | | | | | | This patch correctly enable and disable asynchronous cancellation on Linux posix_spawn. Current code invert the logic by enabling and disabling instead. It also adds a new test to check if posix_spawn is not a cancellation entrypoint. Checked on x86_64, i686, powerpc64le, and aarch64. * nptl/Makefile (tests): Add tst-exec5. * nptl/tst-exec5.c: New file. * sysdeps/unix/sysv/linux/spawni.c (__spawni): Correctly enable and disable asynchronous cancellation.
* powerpc: Fix POWER9 impliesTulio Magno Quites Machado Filho2016-09-193-2/+9
| | | | | | | Fix multiarch build for POWER9 by correcting the order of the directories listed at sysnames configure variable. (cherry picked from commit 1850ce5a2ea3b908b26165e7e951cd4334129f07)
* NaCl: Fix libc.abilist missing GLIBC_2.24 A.Roland McGrath2016-09-022-0/+3
| | | | * sysdeps/arm/nacl/libc.abilist: Add GLIBC_2.24 A.
* NaCl: Fix compile error for __dup after libc_hidden_proto addition.Roland McGrath2016-09-022-0/+5
| | | | | | * sysdeps/nacl/dup.c: Add libc_hidden_def. (cherry picked from commit 6b75ba1388bff6a81bad410d7318d385a043b3cb)
* Fix generic wait3 after union wait_status removal.Roland McGrath2016-09-022-1/+6
| | | | | | | * sysdeps/posix/wait3.c: Don't treat STAT_LOC as a union, since it's not any more. (cherry picked from commit 9a3d16ac152447567bfc822497c564a0630c79fe)
* NaCl: Fix compile error in clock function.Roland McGrath2016-09-022-1/+5
| | | | | | * sysdeps/nacl/clock.c (clock): nacl_abi_clock_t -> nacl_irt_clock_t (cherry picked from commit 307c2c2dfff76330a29a3ab69a0177b118142145)
* nptl/tst-once5: Reduce time to expected failureFlorian Weimer2016-08-182-0/+7
| | | | (cherry picked from commit 1f645571d2db9008b3cd3d5acb9ff93357864283)
* argp: Do not override GCC keywords with macros [BZ #16907]Florian Weimer2016-08-183-55/+14
| | | | | | | | | | | | | glibc provides fallback definitions already. It is not necessary to suppress warnings for unknown attributes because GCC does this automatically for system headers. This commit does not sync with gnulib because gnulib has started to use _GL_* macros in the header file, which are arguably in the gnulib implementation space and not suitable for an installed glibc header file. (cherry picked from commit 2c820533c61fed175390bc6058afbbe42d2edc37)
* arm: mark __startcontext as .cantunwind (bug 20435)Andreas Schwab2016-08-183-0/+24
| | | | | | | | | | | __startcontext marks the bottom of the call stack of the contexts created by makecontext. (cherry picked from commit 9e2ff6c9cc54c0b4402b8d49e4abe7000fde7617) Also includes the NEWS update, cherry-picked from commits 056dd72af83f5459ce6d545a49dea6dba7d635dc and 4d047efdbc55b0d68947cde682e5363d16a66294.
* Do not override objects in libc.a in other static libraries [BZ #20452]Florian Weimer2016-08-1814-1/+50
| | | | | | | With this change, we no longer add sysdep.o and similar objects which are present in libc.a to other static libraries. (cherry picked from commit d9067fca40b8aac156d73cfa44d6875813555a6c)
* sparc: remove fdim sparc specific implementationsAurelien Jarno2016-08-1512-314/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fdim and fdimf functions on sparc do not fully follow the standard and do not set errno to ERANGE when the result overflows. Since glibc 2.24 this causes the two following tests to fail: Failure: fdim (max_value, -max_value): errno set to 0, expected 34 (ERANGE) Failure: fdim_upward (max_value, -max_value): errno set to 0, expected 34 (ERANGE) It happens that using GCC with the generic C code generates very similar code to the sparc specific implementations. Therefore this patches remove them. Note it might still worth adding a vis3 specific version of fdim on sparc32/sparcv9, this is done in a following patch to ease backporting. Changelog: * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile [$(subdir) = math && $(have-as-vis3) = yes] (libm-sysdep_routines): Remove s_fdimf-vis3, s_fdim-vis3. * sysdeps/sparc/sparc32/fpu/s_fdim.S: Delete file. * sysdeps/sparc/sparc32/fpu/s_fdimf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_fdim.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_fdimf.S: Likewise. (cherry picked from commit 8a9f4eb95894eae7e725e79721ba26fbc5b4ed06)
* Fix sNaN handling in nearbyint on 32-bit sparc.David S. Miller2016-08-155-10/+22
| | | | | | | | | | | | | | * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S (__nearbyint_vis3): Don't check for sNaN before float register is loaded with the incoming argument. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S (__nearbyintf_vis3): Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint): Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf): Likewise. (cherry picked from commit 3ef3f1b93fdf20143865cc16dd75f39a7f0fac2f)
* powerpc: fix ifunc-sel.h fix asm constraints and clobber listAurelien Jarno2016-08-142-2/+8
| | | | | | | | | | | | | | | | | As pointer out on the mailing list, the inline assembly code in sysdeps/powerpc/ifunc-sel.h doesn't have a list of clobbered registers and used wrong constraints. This patch fixes that. I verified it doesn't introduce any change in the generated code. Changelog: * sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Add "11", "12", "cr0" to the clobber list. Use "i" constraint instead of "X". (ifunc_one): Add "12" to the clobber list. Use "i" constraint instead of "X". (cherry picked from commit 30f926d3b3dcb74c038155715ed341d5c4b334eb)
* powerpc: fix ifunc-sel.h with GCC 6Aurelien Jarno2016-08-142-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-bit PowerPC GCC 6 always saves the PIC register on the stack in the prologue and adjust the stack in the epilogue. It is therefore not possible anymore to just exit the function in the inline asm code, otherwise it corrupts the stack pointer. This causes the following tests to fail when using GCC 6: FAIL: elf/ifuncmain1 FAIL: elf/ifuncmain1pic FAIL: elf/ifuncmain1picstatic FAIL: elf/ifuncmain1pie FAIL: elf/ifuncmain1staticpic FAIL: elf/ifuncmain1staticpie FAIL: elf/ifuncmain1vis FAIL: elf/ifuncmain1vispic FAIL: elf/ifuncmain1vispie FAIL: elf/ifuncmain2pic FAIL: elf/ifuncmain2picstatic FAIL: elf/ifuncmain3 FAIL: elf/ifuncmain4picstatic FAIL: elf/ifuncmain5 FAIL: elf/ifuncmain5picstatic FAIL: elf/ifuncmain5staticpic The solution is to replace the beqlr instructions by a beq to the end of the inline asm code. This fixes all the above failures. ChangeLog: * sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Replace beqlr instructions by beq instructions jumping to the end of the function. (cherry picked from commit ee71e5b6dd6a21e981ad0fa74359e066f5a8b359)
* Update from Translation Project.Carlos O'Donell2016-08-044-131/+114
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* malloc: Preserve arena free list/thread count invariant [BZ #20370]Florian Weimer2016-08-042-5/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is necessary to preserve the invariant that if an arena is on the free list, it has thread attach count zero. Otherwise, when arena_thread_freeres sees the zero attach count, it will add it, and without the invariant, an arena could get pushed to the list twice, resulting in a cycle. One possible execution trace looks like this: Thread 1 examines free list and observes it as empty. Thread 2 exits and adds its arena to the free list, with attached_threads == 0). Thread 1 selects this arena in reused_arena (not from the free list). Thread 1 increments attached_threads and attaches itself. (The arena remains on the free list.) Thread 1 exits, decrements attached_threads, and adds the arena to the free list. The final step creates a cycle in the usual way (by overwriting the next_free member with the former list head, while there is another list item pointing to the arena structure). tst-malloc-thread-exit exhibits this issue, but it was only visible with a debugger because the incorrect fix in bug 19243 removed the assert from get_free_list. (cherry picked from commit f88aab5d508c13ae4a88124e65773d7d827cd47b)
* x86: Use sysdep.o from libc.a in static librariesFlorian Weimer2016-08-042-0/+9
| | | | | | | | | | | Static libraries can use the sysdep.o copy in libc.a without a performance penalty. This results in a visible difference if libpthread.a is relinked into a single object file (which is needed to support libraries which check for the presence of certain symbols to enable threading support, which generally fails with static linking unless libpthread.a is relinked). (cherry picked from commit e67330ab57bfd0f964539576ae7dcc658c456724)
* Update for glibc 2.24 release.glibc-2.24Carlos O'Donell2016-08-013-3/+7
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* Update libc.pot and NEWS.Carlos O'Donell2016-08-013-187/+425
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* sparc: remove ceil, floor, trunc sparc specific implementationsAurelien Jarno2016-08-0247-2245/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ceil, floor and trunc functions on sparc do not fully follow the standard and trigger an inexact exception when presented a value which is not an integer. Since glibc 2.24 this causes a few tests to fail, for instance: testing double (without inline functions) Failure: ceil (lit_pi): Exception "Inexact" set Failure: ceil (-lit_pi): Exception "Inexact" set Failure: ceil (min_subnorm_value): Exception "Inexact" set Failure: ceil (min_value): Exception "Inexact" set Failure: ceil (0.1): Exception "Inexact" set Failure: ceil (0.25): Exception "Inexact" set Failure: ceil (0.625): Exception "Inexact" set Failure: ceil (-min_subnorm_value): Exception "Inexact" set Failure: ceil (-min_value): Exception "Inexact" set Failure: ceil (-0.1): Exception "Inexact" set Failure: ceil (-0.25): Exception "Inexact" set Failure: ceil (-0.625): Exception "Inexact" set I tried to fix that by using the same strategy than used on other architectures, that is by saving the FSR register at the beginning and restoring it at the end of the function. When doing so I noticed a comment that this operation might be very costly, so I decided to do some benchmarks. The benchmarks below represent the time required to run each of the function 60 millions of times with different input value. I have done that in the basic V9 code, the VIS2 code, and using the default C implementation of the libc, for both sparc32 and sparc64, on a Niagara T1 based machine and an UltraSparc IIIi. Given I don't have access to a more recent machine), I haven't been able to test the VIS3 version. Also it should be noted that it doesn't make sense to do this benchmark for V8 or earlier as in that case we use the default C implementation. The results are available in the table below, the "+ fix" version correspond to the one saving and restoring the FSR. Niagara T1 / sparc32 -------------------- ceilf ceil floorf floor truncf trunc V9 19.10 22.48 19.10 22.48 16.59 19.27 V9 + fix 19.77 23.34 19.77 23.33 17.27 20.12 VIS2 16.87 19.62 16.87 19.62 VIS2 + fix 17.55 20.47 17.55 20.47 C impl 11.39 13.80 11.40 13.80 10.88 10.84 Niagara T1 / sparc64 -------------------- ceilf ceil floorf floor truncf trunc V9 18.14 22.23 18.14 22.23 15.64 19.02 V9 + fix 18.82 23.08 18.82 23.08 16.32 19.87 VIS2 15.92 19.37 15.92 19.37 VIS2 + fix 16.59 20.22 16.59 20.22 C impl 11.39 13.60 11.39 15.36 10.88 12.65 UltraSparc IIIi / sparc32 ------------------------- ceilf ceil floorf floor truncf trunc V9 4.81 7.09 6.61 11.64 4.91 7.05 V9 + fix 7.20 10.42 7.14 10.54 6.76 9.47 VIS2 4.81 7.03 4.76 7.13 VIS2 + fix 6.76 9.51 6.71 9.63 C impl 3.88 8.62 3.90 9.45 3.57 6.62 UltraSparc IIIi / sparc64 ------------------------- ceilf ceil floorf floor truncf trunc V9 3.48 4.39 3.48 4.41 3.01 3.85 V9 + fix 4.76 5.90 4.76 5.90 4.86 6.26 VIS2 2.95 3.61 2.95 3.61 VIS2 + fix 4.24 5.37 4.30 7.97 C impl 3.63 4.89 3.62 6.38 3.33 4.03 The first thing that should be noted is that the C implementation is always faster on the Niagara T1 based machine. On the UltraSparc IIIi the float version on sparc32 is also faster. Coming back about the fix saving and restoring the FSR, it appears it has a big impact as expected. In that case the C implementation is always faster than the fixed implementations. This patch therefore removes the sparc specific implementations in favor of the generic ones. Changelog: * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile [$(subdir) = math] (libm-sysdep_routines): Remove. [$(subdir) = math && $(have-as-vis3) = yes] (libm-sysdep_routines): Remove s_ceilf-vis3, s_ceil-vis3, s_floorf-vis3, s_floor-vis3, s_truncf-vis3, s_trunc-vis3. * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S: Delete file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_floor.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_floorf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_ceil.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_ceilf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_floor.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_floorf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_trunc.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_truncf.S: Likewise.
* CVE-2016-5417 was assigned to bug 19257Florian Weimer2016-07-291-0/+5
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