diff options
Diffstat (limited to 'sysdeps/powerpc/powerpc64')
29 files changed, 200 insertions, 200 deletions
diff --git a/sysdeps/powerpc/powerpc64/fpu/s_ceill.S b/sysdeps/powerpc/powerpc64/fpu/s_ceill.S index bffac3962c..3ef7b9f174 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_ceill.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_ceill.S @@ -69,7 +69,7 @@ ENTRY (__ceill) mtfsf 0x01,fp11 /* restore previous rounding mode. */ fnabs fp1,fp1 /* if (x == 0.0) */ blr /* x = -0.0; */ - + /* The high double is > TWO52 so we need to round the low double and perhaps the high double. In this case we have to round the low double and handle any adjustment to the high double that may be @@ -93,7 +93,7 @@ ENTRY (__ceill) beqlr- cr0 mtfsfi 7,2 /* Set rounding mode toward +inf. */ fdiv fp8,fp1,fp13 /* x_high/TWO52 */ - + bng- cr6,.L6 /* if (x > 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ @@ -110,7 +110,7 @@ ENTRY (__ceill) b .L9 .L6: /* if (x < 0.0) */ fctidz fp0,fp8 - fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ + fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ bnl cr5,.L7 /* if (x_low < 0.0) */ fmr fp3,fp1 fmr fp4,fp2 diff --git a/sysdeps/powerpc/powerpc64/fpu/s_floor.S b/sysdeps/powerpc/powerpc64/fpu/s_floor.S index a8e79e9361..44bd83233b 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_floor.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_floor.S @@ -48,7 +48,7 @@ EALIGN (__floor, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__floor) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_floorf.S b/sysdeps/powerpc/powerpc64/fpu/s_floorf.S index f65e3b8a70..a0a22e7eb9 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_floorf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_floorf.S @@ -47,7 +47,7 @@ EALIGN (__floorf, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__floorf) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/fpu/s_isnan.S index 3fd62ae51d..95eb81eef4 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_isnan.S @@ -21,7 +21,7 @@ /* int __isnan(x) */ .machine power4 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 mffs fp0 mtfsb0 4*cr6+lt /* reset_fpscr_bit (FPSCR_VE) */ diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llrint.S b/sysdeps/powerpc/powerpc64/fpu/s_llrint.S index 82b8df41d4..7019347b52 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llrint.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llrint.S @@ -20,14 +20,14 @@ #include <math_ldbl_opt.h> /* long long int[r3] __llrint (double x[fp1]) */ -ENTRY (__llrint) +ENTRY (__llrint) CALL_MCOUNT 0 fctid fp13,fp1 stfd fp13,-16(r1) nop /* Insure the following load is in a different dispatch group */ nop /* to avoid pipe stall on POWER4&5. */ nop - ld r3,-16(r1) + ld r3,-16(r1) blr END (__llrint) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S b/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S index 3de36c22fa..467396722f 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S @@ -19,14 +19,14 @@ #include <sysdep.h> /* long long int[r3] __llrintf (float x[fp1]) */ -ENTRY (__llrintf) +ENTRY (__llrintf) CALL_MCOUNT 0 fctid fp13,fp1 stfd fp13,-16(r1) nop /* Insure the following load is in a different dispatch group */ nop /* to avoid pipe stall on POWER4&5. */ nop - ld r3,-16(r1) + ld r3,-16(r1) blr END (__llrintf) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llround.S b/sysdeps/powerpc/powerpc64/fpu/s_llround.S index 286aae3d6a..54b8341b4e 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llround.S @@ -25,13 +25,13 @@ .LC1: /* 0.5 */ .tc FD_3fe00000_0[TC],0x3fe0000000000000 .section ".text" - + /* long long [r3] llround (double x [fp1]) - IEEE 1003.1 llround function. IEEE specifies "round to the nearest + IEEE 1003.1 llround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "round to Nearest" mode. Instead we set "round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S b/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S index b1083a81a6..25c61f2459 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S @@ -24,13 +24,13 @@ .LC1: /* 0.5 */ .tc FD_3fe00000_0[TC],0x3fe0000000000000 .section ".text" - + /* long long [r3] llroundf (float x [fp1]) - IEEE 1003.1 llroundf function. IEEE specifies "roundf to the nearest + IEEE 1003.1 llroundf function. IEEE specifies "roundf to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "roundf to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "roundf to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "round to Nearest" mode. Instead we set "round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. diff --git a/sysdeps/powerpc/powerpc64/fpu/s_round.S b/sysdeps/powerpc/powerpc64/fpu/s_round.S index 022be84a28..3c7437a8f4 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_round.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_round.S @@ -25,13 +25,13 @@ .LC1: /* 0.5 */ .tc FD_3fe00000_0[TC],0x3fe0000000000000 .section ".text" - + /* double [fp1] round (double x [fp1]) - IEEE 1003.1 round function. IEEE specifies "round to the nearest + IEEE 1003.1 round function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "Round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "Round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "Round to Nearest" mode. Instead we set "Round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. */ @@ -63,7 +63,7 @@ EALIGN (__round, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__round) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_roundf.S b/sysdeps/powerpc/powerpc64/fpu/s_roundf.S index dc50d1a77e..980a77bde0 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_roundf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_roundf.S @@ -24,13 +24,13 @@ .LC1: /* 0.5 */ .tc FD_3f000000_0[TC],0x3f00000000000000 .section ".text" - + /* float [fp1] roundf (float x [fp1]) - IEEE 1003.1 round function. IEEE specifies "round to the nearest + IEEE 1003.1 round function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "Round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "Round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "Round to Nearest" mode. Instead we set "Round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. */ @@ -62,7 +62,7 @@ EALIGN (__roundf, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__roundf) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_roundl.S b/sysdeps/powerpc/powerpc64/fpu/s_roundl.S index 5cc41c03ce..547b72150d 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_roundl.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_roundl.S @@ -91,7 +91,7 @@ ENTRY (__roundl) beqlr- cr0 mtfsfi 7,1 /* Set rounding mode toward 0. */ fdiv fp8,fp1,fp13 /* x_high/TWO52 */ - + bng- cr6,.L6 /* if (x > 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ @@ -109,7 +109,7 @@ ENTRY (__roundl) b .L9 .L6: /* if (x < 0.0) */ fctidz fp0,fp8 - fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ + fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ bnl cr5,.L7 /* if (x_low < 0.0) */ fmr fp3,fp1 fmr fp4,fp2 diff --git a/sysdeps/powerpc/powerpc64/fpu/s_trunc.S b/sysdeps/powerpc/powerpc64/fpu/s_trunc.S index 5b018fb3eb..f123873666 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_trunc.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_trunc.S @@ -23,10 +23,10 @@ .LC0: /* 2**52 */ .tc FD_43300000_0[TC],0x4330000000000000 .section ".text" - + /* double [fp1] trunc (double x [fp1]) IEEE 1003.1 trunc function. IEEE specifies "trunc to the integer - value, in floating format, nearest to but no larger in magnitude + value, in floating format, nearest to but no larger in magnitude then the argument." We set "round toward Zero" mode and trunc by adding +-2**52 then subtracting +-2**52. */ diff --git a/sysdeps/powerpc/powerpc64/fpu/s_truncf.S b/sysdeps/powerpc/powerpc64/fpu/s_truncf.S index 9f35240241..5ea5f3d04a 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_truncf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_truncf.S @@ -22,10 +22,10 @@ .LC0: /* 2**23 */ .tc FD_4b000000_0[TC],0x4b00000000000000 .section ".text" - + /* float [fp1] truncf (float x [fp1]) IEEE 1003.1 trunc function. IEEE specifies "trunc to the integer - value, in floating format, nearest to but no larger in magnitude + value, in floating format, nearest to but no larger in magnitude then the argument." We set "round toward Zero" mode and trunc by adding +-2**23 then subtracting +-2**23. */ diff --git a/sysdeps/powerpc/powerpc64/fpu/s_truncl.S b/sysdeps/powerpc/powerpc64/fpu/s_truncl.S index 03f45270a2..06fd7dbe4d 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_truncl.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_truncl.S @@ -79,7 +79,7 @@ ENTRY (__truncl) beqlr- cr0 mtfsfi 7,1 /* Set rounding mode toward 0. */ fdiv fp8,fp1,fp13 /* x_high/TWO52 */ - + bng- cr6,.L6 /* if (x > 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ @@ -98,7 +98,7 @@ ENTRY (__truncl) .L6: /* if (x < 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ - fadd fp8,fp8,fp8 /* tau++; Make tau even */ + fadd fp8,fp8,fp8 /* tau++; Make tau even */ bnl cr5,.L7 /* if (x_low < 0.0) */ fmr fp3,fp1 fmr fp4,fp2 diff --git a/sysdeps/powerpc/powerpc64/hp-timing.c b/sysdeps/powerpc/powerpc64/hp-timing.c index f54a5f879b..5073adb0e5 100644 --- a/sysdeps/powerpc/powerpc64/hp-timing.c +++ b/sysdeps/powerpc/powerpc64/hp-timing.c @@ -1,4 +1,4 @@ -/* Support for high precision, low overhead timing functions. +/* Support for high precision, low overhead timing functions. powerpc64 version. Copyright (C) 2005-2013 Free Software Foundation, Inc. This file is part of the GNU C Library. diff --git a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c index bd0f9f04f5..78bba57a28 100644 --- a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c +++ b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c @@ -35,10 +35,10 @@ __sqrt (double x) /* wrapper sqrt */ #else if (__builtin_expect (_LIB_VERSION == _IEEE_, 0)) return z; - + if (__builtin_expect (x != x, 0)) return z; - + if (__builtin_expect (x < 0.0, 0)) return __kernel_standard (x, x, 26); /* sqrt(negative) */ else diff --git a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c index 07c4dc1565..12d9f6273d 100644 --- a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c +++ b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c @@ -38,10 +38,10 @@ __sqrtf (float x) /* wrapper sqrtf */ if (__builtin_expect (_LIB_VERSION == _IEEE_, 0)) return z; - + if (__builtin_expect (x != x, 0)) return z; - + if (__builtin_expect (x < 0.0, 0)) /* sqrtf(negative) */ return (float) __kernel_standard ((double) x, (double) x, 126); diff --git a/sysdeps/powerpc/powerpc64/power4/memcmp.S b/sysdeps/powerpc/powerpc64/power4/memcmp.S index 6378ecb2d9..69caedc9ff 100644 --- a/sysdeps/powerpc/powerpc64/power4/memcmp.S +++ b/sysdeps/powerpc/powerpc64/power4/memcmp.S @@ -51,17 +51,17 @@ EALIGN (memcmp, 4, 0) /* If less than 8 bytes or not aligned, use the unaligned byte loop. */ blt cr1, L(bytealigned) - std rWORD8,-8(r1) + std rWORD8,-8(r1) cfi_offset(rWORD8,-8) - std rWORD7,-16(r1) + std rWORD7,-16(r1) cfi_offset(rWORD7,-16) bne L(unaligned) /* At this point we know both strings have the same alignment and the compare length is at least 8 bytes. rBITDIF contains the low order 3 bits of rSTR1 and cr5 contains the result of the logical compare - of rBITDIF to 0. If rBITDIF == 0 then we are already double word + of rBITDIF to 0. If rBITDIF == 0 then we are already double word aligned and can perform the DWaligned loop. - + Otherwise we know the two strings have the same alignment (but not yet DW). So we can force the string addresses to the next lower DW boundary and special case this first DW word using shift left to @@ -141,7 +141,7 @@ L(DWaligned): beq L(dP4) bgt cr1, L(dP3) beq cr1, L(dP2) - + /* Remainder is 8 */ .align 4 L(dP1): @@ -150,7 +150,7 @@ L(dP1): (8-15 byte compare), we want to use only volatile registers. This means we can avoid restoring non-volatile registers since we did not change any on the early exit path. The key here is the non-early - exit path only cares about the condition code (cr5), not about which + exit path only cares about the condition code (cr5), not about which register pair was used. */ ld rWORD5, 0(rSTR1) ld rWORD6, 0(rSTR2) @@ -168,7 +168,7 @@ L(dP1e): cmpld cr6, rWORD5, rWORD6 bne cr5, L(dLcr5) bne cr0, L(dLcr0) - + ldu rWORD7, 32(rSTR1) ldu rWORD8, 32(rSTR2) bne cr1, L(dLcr1) @@ -185,7 +185,7 @@ L(dP1x): bne L(d00) li rRTN, 0 blr - + /* Remainder is 16 */ .align 4 L(dP2): @@ -226,7 +226,7 @@ L(dP2x): bne L(d00) li rRTN, 0 blr - + /* Remainder is 24 */ .align 4 L(dP3): @@ -268,7 +268,7 @@ L(dP3x): bne L(d00) li rRTN, 0 blr - + /* Count is a multiple of 32, remainder is 0 */ .align 4 L(dP4): @@ -311,8 +311,8 @@ L(dLoop3): ldu rWORD8, 32(rSTR2) bne- cr1, L(dLcr1) cmpld cr0, rWORD1, rWORD2 - bdnz+ L(dLoop) - + bdnz+ L(dLoop) + L(dL4): cmpld cr1, rWORD3, rWORD4 bne cr6, L(dLcr6) @@ -327,7 +327,7 @@ L(d24): bne cr6, L(dLcr6) L(d14): sldi. r12, rN, 3 - bne cr5, L(dLcr5) + bne cr5, L(dLcr5) L(d04): ld rWORD8,-8(r1) ld rWORD7,-16(r1) @@ -338,7 +338,7 @@ L(d04): shift right double to eliminate bits beyond the compare length. */ L(d00): ld rWORD1, 8(rSTR1) - ld rWORD2, 8(rSTR2) + ld rWORD2, 8(rSTR2) srd rWORD1, rWORD1, rN srd rWORD2, rWORD2, rN cmpld cr5, rWORD1, rWORD2 @@ -378,22 +378,22 @@ L(dLcr5x): bgtlr cr5 li rRTN, -1 blr - + .align 4 L(bytealigned): mtctr rN /* Power4 wants mtctr 1st in dispatch group */ beq- cr6, L(zeroLength) /* We need to prime this loop. This loop is swing modulo scheduled - to avoid pipe delays. The dependent instruction latencies (load to + to avoid pipe delays. The dependent instruction latencies (load to compare to conditional branch) is 2 to 3 cycles. In this loop each dispatch group ends in a branch and takes 1 cycle. Effectively - the first iteration of the loop only serves to load operands and - branches based on compares are delayed until the next loop. + the first iteration of the loop only serves to load operands and + branches based on compares are delayed until the next loop. So we must precondition some registers and condition codes so that we don't exit the loop early on the first iteration. */ - + lbz rWORD1, 0(rSTR1) lbz rWORD2, 0(rSTR2) bdz- L(b11) @@ -413,7 +413,7 @@ L(bLoop): cmpld cr6, rWORD5, rWORD6 bdz- L(b3i) - + lbzu rWORD3, 1(rSTR1) lbzu rWORD4, 1(rSTR2) bne- cr1, L(bLcr1) @@ -427,10 +427,10 @@ L(bLoop): cmpld cr1, rWORD3, rWORD4 bdnz+ L(bLoop) - + /* We speculatively loading bytes before we have tested the previous bytes. But we must avoid overrunning the length (in the ctr) to - prevent these speculative loads from causing a segfault. In this + prevent these speculative loads from causing a segfault. In this case the loop will exit early (before the all pending bytes are tested. In this case we must complete the pending operations before returning. */ @@ -474,14 +474,14 @@ L(bx56): nop L(b12): bne- cr0, L(bx12) -L(bx34): +L(bx34): sub rRTN, rWORD3, rWORD4 blr L(b11): L(bx12): sub rRTN, rWORD1, rWORD2 blr - .align 4 + .align 4 L(zeroLengthReturn): ld rWORD8,-8(r1) ld rWORD7,-16(r1) @@ -493,9 +493,9 @@ L(zeroLength): /* At this point we know the strings have different alignment and the compare length is at least 8 bytes. rBITDIF contains the low order 3 bits of rSTR1 and cr5 contains the result of the logical compare - of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word + of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word aligned and can perform the DWunaligned loop. - + Otherwise we know that rSTR1 is not already DW aligned yet. So we can force the string addresses to the next lower DW boundary and special case this first DW word using shift left to @@ -515,14 +515,14 @@ L(zeroLength): #define rE r0 /* Right rotation temp for rWORD6. */ #define rG r12 /* Right rotation temp for rWORD8. */ L(unaligned): - std r29,-24(r1) + std r29,-24(r1) cfi_offset(r29,-24) clrldi rSHL, rSTR2, 61 beq- cr6, L(duzeroLength) - std r28,-32(r1) + std r28,-32(r1) cfi_offset(r28,-32) beq cr5, L(DWunaligned) - std r27,-40(r1) + std r27,-40(r1) cfi_offset(r27,-40) /* Adjust the logical start of rSTR2 ro compensate for the extra bits in the 1st rSTR1 DW. */ @@ -530,19 +530,19 @@ L(unaligned): /* But do not attempt to address the DW before that DW that contains the actual start of rSTR2. */ clrrdi rSTR2, rSTR2, 3 - std r26,-48(r1) + std r26,-48(r1) cfi_offset(r26,-48) /* Compute the left/right shift counts for the unalign rSTR2, - compensating for the logical (DW aligned) start of rSTR1. */ + compensating for the logical (DW aligned) start of rSTR1. */ clrldi rSHL, r27, 61 - clrrdi rSTR1, rSTR1, 3 - std r25,-56(r1) + clrrdi rSTR1, rSTR1, 3 + std r25,-56(r1) cfi_offset(r25,-56) sldi rSHL, rSHL, 3 cmpld cr5, r27, rSTR2 add rN, rN, rBITDIF sldi r11, rBITDIF, 3 - std r24,-64(r1) + std r24,-64(r1) cfi_offset(r24,-64) subfic rSHR, rSHL, 64 srdi rTMP, rN, 5 /* Divide by 32 */ @@ -618,16 +618,16 @@ L(duPs4): compare length is at least 8 bytes. */ .align 4 L(DWunaligned): - std r27,-40(r1) + std r27,-40(r1) cfi_offset(r27,-40) clrrdi rSTR2, rSTR2, 3 - std r26,-48(r1) + std r26,-48(r1) cfi_offset(r26,-48) srdi rTMP, rN, 5 /* Divide by 32 */ - std r25,-56(r1) + std r25,-56(r1) cfi_offset(r25,-56) andi. rBITDIF, rN, 24 /* Get the DW remainder */ - std r24,-64(r1) + std r24,-64(r1) cfi_offset(r24,-64) sldi rSHL, rSHL, 3 ld rWORD6, 0(rSTR2) @@ -641,7 +641,7 @@ L(DWunaligned): mtctr rTMP /* Power4 wants mtctr 1st in dispatch group */ bgt cr1, L(duP3) beq cr1, L(duP2) - + /* Remainder is 8 */ .align 4 L(duP1): @@ -672,7 +672,7 @@ L(duP1e): bne cr0, L(duLcr0) or rWORD6, rE, rF cmpld cr6, rWORD5, rWORD6 - b L(duLoop3) + b L(duLoop3) .align 4 /* At this point we exit early with the first double word compare complete and remainder of 0 to 7 bytes. See L(du14) for details on @@ -736,7 +736,7 @@ L(duP2x): ld rWORD2, 8(rSTR2) srd rA, rWORD2, rSHR b L(dutrim) - + /* Remainder is 24 */ .align 4 L(duP3): @@ -786,7 +786,7 @@ L(duP3x): ld rWORD2, 8(rSTR2) srd rA, rWORD2, rSHR b L(dutrim) - + /* Count is a multiple of 32, remainder is 0 */ .align 4 L(duP4): @@ -852,8 +852,8 @@ L(duLoop3): srd rG, rWORD8, rSHR sld rB, rWORD8, rSHL or rWORD8, rG, rH - bdnz+ L(duLoop) - + bdnz+ L(duLoop) + L(duL4): bne cr1, L(duLcr1) cmpld cr1, rWORD3, rWORD4 @@ -875,7 +875,7 @@ L(du14): This allows the use of double word subtract to compute the final result. - However it may not be safe to load rWORD2 which may be beyond the + However it may not be safe to load rWORD2 which may be beyond the string length. So we compare the bit length of the remainder to the right shift count (rSHR). If the bit count is less than or equal we do not need to load rWORD2 (all significant bits are already in @@ -890,16 +890,16 @@ L(du14): L(dutrim): ld rWORD1, 8(rSTR1) ld rWORD8,-8(r1) - subfic rN, rN, 64 /* Shift count is 64 - (rN * 8). */ + subfic rN, rN, 64 /* Shift count is 64 - (rN * 8). */ or rWORD2, rA, rB - ld rWORD7,-16(r1) + ld rWORD7,-16(r1) ld r29,-24(r1) srd rWORD1, rWORD1, rN srd rWORD2, rWORD2, rN - ld r28,-32(r1) + ld r28,-32(r1) ld r27,-40(r1) li rRTN, 0 - cmpld cr0, rWORD1, rWORD2 + cmpld cr0, rWORD1, rWORD2 ld r26,-48(r1) ld r25,-56(r1) beq cr0, L(dureturn24) @@ -913,7 +913,7 @@ L(duLcr0): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr0, L(dureturn29) + bgt cr0, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -923,7 +923,7 @@ L(duLcr1): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr1, L(dureturn29) + bgt cr1, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -933,7 +933,7 @@ L(duLcr6): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr6, L(dureturn29) + bgt cr6, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -943,7 +943,7 @@ L(duLcr5): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr5, L(dureturn29) + bgt cr5, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -955,14 +955,14 @@ L(duZeroReturn): L(dureturn): ld rWORD8,-8(r1) ld rWORD7,-16(r1) -L(dureturn29): +L(dureturn29): ld r29,-24(r1) ld r28,-32(r1) -L(dureturn27): +L(dureturn27): ld r27,-40(r1) -L(dureturn26): +L(dureturn26): ld r26,-48(r1) -L(dureturn25): +L(dureturn25): ld r25,-56(r1) L(dureturn24): ld r24,-64(r1) diff --git a/sysdeps/powerpc/powerpc64/power4/memcpy.S b/sysdeps/powerpc/powerpc64/power4/memcpy.S index c43d1d2e4e..4317c7e786 100644 --- a/sysdeps/powerpc/powerpc64/power4/memcpy.S +++ b/sysdeps/powerpc/powerpc64/power4/memcpy.S @@ -21,10 +21,10 @@ /* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]); Returns 'dst'. - Memcpy handles short copies (< 32-bytes) using a binary move blocks - (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled - with the appropriate combination of byte and halfword load/stores. - There is minimal effort to optimize the alignment of short moves. + Memcpy handles short copies (< 32-bytes) using a binary move blocks + (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled + with the appropriate combination of byte and halfword load/stores. + There is minimal effort to optimize the alignment of short moves. The 64-bit implementations of POWER3 and POWER4 do a reasonable job of handling unaligned load/stores that do not cross 32-byte boundaries. @@ -47,13 +47,13 @@ EALIGN (memcpy, 5, 0) clrldi 10,4,61 /* check alignment of src. */ cmpldi cr6,5,8 ble- cr1,.L2 /* If move < 32 bytes use short move code. */ - cmpld cr6,10,11 + cmpld cr6,10,11 mr 12,4 srdi 9,5,3 /* Number of full double words remaining. */ mtcrf 0x01,0 mr 31,5 beq .L0 - + subf 31,0,5 /* Move 0-7 bytes as needed to get the destination doubleword aligned. */ 1: bf 31,2f @@ -74,15 +74,15 @@ EALIGN (memcpy, 5, 0) 0: clrldi 10,12,61 /* check alignment of src again. */ srdi 9,31,3 /* Number of full double words remaining. */ - + /* Copy doublewords from source to destination, assuming the destination is aligned on a doubleword boundary. At this point we know there are at least 25 bytes left (32-7) to copy. - The next step is to determine if the source is also doubleword aligned. + The next step is to determine if the source is also doubleword aligned. If not branch to the unaligned move code at .L6. which uses a load, shift, store strategy. - + Otherwise source and destination are doubleword aligned, and we can the optimized doubleword copy loop. */ .L0: @@ -95,14 +95,14 @@ EALIGN (memcpy, 5, 0) Use a unrolled loop to copy 4 doubleword (32-bytes) per iteration. If the copy is not an exact multiple of 32 bytes, 1-3 doublewords are copied as needed to set up the main loop. After - the main loop exits there may be a tail of 1-7 bytes. These byte are + the main loop exits there may be a tail of 1-7 bytes. These byte are copied a word/halfword/byte at a time as needed to preserve alignment. */ srdi 8,31,5 cmpldi cr1,9,4 cmpldi cr6,11,0 mr 11,12 - + bf 30,1f ld 6,0(12) ld 7,8(12) @@ -113,7 +113,7 @@ EALIGN (memcpy, 5, 0) addi 10,3,16 bf 31,4f ld 0,16(12) - std 0,16(3) + std 0,16(3) blt cr1,3f addi 11,12,24 addi 10,3,24 @@ -127,7 +127,7 @@ EALIGN (memcpy, 5, 0) addi 11,12,8 std 6,0(3) addi 10,3,8 - + .align 4 4: ld 6,0(11) @@ -142,7 +142,7 @@ EALIGN (memcpy, 5, 0) std 0,24(10) addi 10,10,32 bdnz 4b -3: +3: rldicr 0,31,0,60 mtcrf 0x01,31 @@ -150,7 +150,7 @@ EALIGN (memcpy, 5, 0) .L9: add 3,3,0 add 12,12,0 - + /* At this point we have a tail of 0-7 bytes and we know that the destination is double word aligned. */ 4: bf 29,2f @@ -171,29 +171,29 @@ EALIGN (memcpy, 5, 0) ld 31,-8(1) ld 3,-16(1) blr - -/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 - bytes. Each case is handled without loops, using binary (1,2,4,8) - tests. - + +/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 + bytes. Each case is handled without loops, using binary (1,2,4,8) + tests. + In the short (0-8 byte) case no attempt is made to force alignment - of either source or destination. The hardware will handle the - unaligned load/stores with small delays for crossing 32- 64-byte, and + of either source or destination. The hardware will handle the + unaligned load/stores with small delays for crossing 32- 64-byte, and 4096-byte boundaries. Since these short moves are unlikely to be - unaligned or cross these boundaries, the overhead to force + unaligned or cross these boundaries, the overhead to force alignment is not justified. - + The longer (9-31 byte) move is more likely to cross 32- or 64-byte boundaries. Since only loads are sensitive to the 32-/64-byte - boundaries it is more important to align the source then the + boundaries it is more important to align the source then the destination. If the source is not already word aligned, we first - move 1-3 bytes as needed. Since we are only word aligned we don't - use double word load/stores to insure that all loads are aligned. + move 1-3 bytes as needed. Since we are only word aligned we don't + use double word load/stores to insure that all loads are aligned. While the destination and stores may still be unaligned, this is only an issue for page (4096 byte boundary) crossing, which should be rare for these short moves. The hardware handles this - case automatically with a small delay. */ - + case automatically with a small delay. */ + .align 4 .L2: mtcrf 0x01,5 @@ -256,11 +256,11 @@ EALIGN (memcpy, 5, 0) lwz 6,0(12) addi 12,12,4 stw 6,0(3) - addi 3,3,4 + addi 3,3,4 2: /* Move 2-3 bytes. */ bf 30,1f lhz 6,0(12) - sth 6,0(3) + sth 6,0(3) bf 31,0f lbz 7,2(12) stb 7,2(3) @@ -281,7 +281,7 @@ EALIGN (memcpy, 5, 0) mr 12,4 bne cr6,4f /* Would have liked to use use ld/std here but the 630 processors are - slow for load/store doubles that are not at least word aligned. + slow for load/store doubles that are not at least word aligned. Unaligned Load/Store word execute with only a 1 cycle penalty. */ lwz 6,0(4) lwz 7,4(4) @@ -297,14 +297,14 @@ EALIGN (memcpy, 5, 0) 6: bf 30,5f lhz 7,4(4) - sth 7,4(3) + sth 7,4(3) bf 31,0f lbz 8,6(4) stb 8,6(3) ld 3,-16(1) blr .align 4 -5: +5: bf 31,0f lbz 6,4(4) stb 6,4(3) @@ -401,7 +401,7 @@ EALIGN (memcpy, 5, 0) /* calculate and store the final DW */ sld 0,6,10 srd 8,7,9 - or 0,0,8 + or 0,0,8 std 0,0(4) 3: rldicr 0,31,0,60 diff --git a/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S b/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S index 108910e77d..28df006425 100644 --- a/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S @@ -18,13 +18,13 @@ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long long [r3] llround (float x [fp1]) - IEEE 1003.1 llround function. IEEE specifies "round to the nearest + IEEE 1003.1 llround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use Floating Convert to Integer Word with round to zero instruction. */ @@ -32,7 +32,7 @@ .machine "power5" EALIGN (__llround, 4, 0) CALL_MCOUNT 0 - frin fp2, fp1 /* Round to nearest +-0.5. */ + frin fp2, fp1 /* Round to nearest +-0.5. */ fctidz fp3, fp2 /* Convert To Integer DW round toward 0. */ stfd fp3, -16(r1) nop /* Insure the following load is in a different dispatch group */ diff --git a/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S index 3afec2b6b0..8319d6e176 100644 --- a/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S @@ -21,13 +21,13 @@ /* int __isnan(x) */ .machine power5 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 stfd fp1,-8(r1) /* copy FPR to GPR */ lis r0,0x7ff0 nop /* insure the following is in a different */ nop /* dispatch group */ - ld r4,-8(r1) + ld r4,-8(r1) sldi r0,r0,32 /* const long r0 0x7ff00000 00000000 */ clrldi r4,r4,1 /* x = fabs(x) */ cmpd cr7,r4,r0 /* if (fabs(x) <= inf) */ diff --git a/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S index 8f0c80662c..d4515d69d2 100644 --- a/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S @@ -21,7 +21,7 @@ /* int __isnan(x) */ .machine power6 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 stfd fp1,-8(r1) /* copy FPR to GPR */ ori r1,r1,0 diff --git a/sysdeps/powerpc/powerpc64/power6/memcpy.S b/sysdeps/powerpc/powerpc64/power6/memcpy.S index 55c0d71184..db29e2b065 100644 --- a/sysdeps/powerpc/powerpc64/power6/memcpy.S +++ b/sysdeps/powerpc/powerpc64/power6/memcpy.S @@ -21,22 +21,22 @@ /* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]); Returns 'dst'. - Memcpy handles short copies (< 32-bytes) using a binary move blocks - (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled - with the appropriate combination of byte and halfword load/stores. - There is minimal effort to optimize the alignment of short moves. + Memcpy handles short copies (< 32-bytes) using a binary move blocks + (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled + with the appropriate combination of byte and halfword load/stores. + There is minimal effort to optimize the alignment of short moves. The 64-bit implementations of POWER3 and POWER4 do a reasonable job of handling unaligned load/stores that do not cross 32-byte boundaries. Longer moves (>= 32-bytes) justify the effort to get at least the destination doubleword (8-byte) aligned. Further optimization is possible when both source and destination are doubleword aligned. - Each case has a optimized unrolled loop. - + Each case has a optimized unrolled loop. + For POWER6 unaligned loads will take a 20+ cycle hiccup for any L1 cache miss that crosses a 32- or 128-byte boundary. Store is more forgiving and does not take a hiccup until page or - segment boundaries. So we require doubleword alignment for + segment boundaries. So we require doubleword alignment for the source but may take a risk and only require word alignment for the destination. */ @@ -54,10 +54,10 @@ EALIGN (memcpy, 7, 0) cmpldi cr6,5,8 ble- cr1,.L2 /* If move < 32 bytes use short move code. */ mtcrf 0x01,0 - cmpld cr6,10,11 + cmpld cr6,10,11 srdi 9,5,3 /* Number of full double words remaining. */ beq .L0 - + subf 5,0,5 /* Move 0-7 bytes as needed to get the destination doubleword aligned. Duplicate some code to maximize fall-through and minimize agen delays. */ @@ -76,7 +76,7 @@ EALIGN (memcpy, 7, 0) lwz 6,1(4) stw 6,1(3) b 0f - + 2: bf 30,4f lhz 6,0(4) sth 6,0(3) @@ -84,26 +84,26 @@ EALIGN (memcpy, 7, 0) lwz 6,2(4) stw 6,2(3) b 0f - + 4: bf 29,0f lwz 6,0(4) stw 6,0(3) -0: +0: /* Add the number of bytes until the 1st doubleword of dst to src and dst. */ add 4,4,0 add 3,3,0 - + clrldi 10,4,61 /* check alignment of src again. */ srdi 9,5,3 /* Number of full double words remaining. */ - + /* Copy doublewords from source to destination, assuming the destination is aligned on a doubleword boundary. At this point we know there are at least 25 bytes left (32-7) to copy. - The next step is to determine if the source is also doubleword aligned. + The next step is to determine if the source is also doubleword aligned. If not branch to the unaligned move code at .L6. which uses a load, shift, store strategy. - + Otherwise source and destination are doubleword aligned, and we can the optimized doubleword copy loop. */ .align 4 @@ -121,12 +121,12 @@ EALIGN (memcpy, 7, 0) the main loop exits there may be a tail of 1-7 bytes. These byte are copied a word/halfword/byte at a time as needed to preserve alignment. - + For POWER6 the L1 is store-through and the L2 is store-in. The L2 is clocked at half CPU clock so we can store 16 bytes every other cycle. POWER6 also has a load/store bypass so we can do - load, load, store, store every 2 cycles. - + load, load, store, store every 2 cycles. + The following code is sensitive to cache line alignment. Do not make any change with out first making sure they don't result in splitting ld/std pairs across a cache line. */ @@ -271,7 +271,7 @@ L(das_loop): std 8,16+96(10) std 0,24+96(10) ble cr5,L(das_loop_e) - + mtctr 12 .align 4 L(das_loop2): @@ -324,7 +324,7 @@ L(das_loop_e): .align 4 L(das_tail): beq cr1,0f - + L(das_tail2): /* At this point we have a tail of 0-7 bytes and we know that the destination is double word aligned. */ @@ -342,7 +342,7 @@ L(das_tail2): lbz 6,4(4) stb 6,4(3) b 0f - + 2: bf 30,1f lhz 6,0(4) sth 6,0(3) @@ -350,7 +350,7 @@ L(das_tail2): lbz 6,2(4) stb 6,2(3) b 0f - + 1: bf 31,0f lbz 6,0(4) stb 6,0(3) @@ -359,7 +359,7 @@ L(das_tail2): ld 3,-16(1) blr -/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 +/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 bytes. Each case is handled without loops, using binary (1,2,4,8) tests. @@ -419,7 +419,7 @@ L(dus_tail): /* At least 6 bytes left and the source is word aligned. This allows some speculative loads up front. */ /* We need to special case the fall-through because the biggest delays - are due to address computation not being ready in time for the + are due to address computation not being ready in time for the AGEN. */ lwz 6,0(12) lwz 7,4(12) @@ -515,7 +515,7 @@ L(dus_tail4): /* Move 4 bytes. */ L(dus_tail2): /* Move 2-3 bytes. */ bf 30,L(dus_tail1) lhz 6,0(12) - sth 6,0(3) + sth 6,0(3) bf 31,L(dus_tailX) lbz 7,2(12) stb 7,2(3) @@ -550,7 +550,7 @@ L(dus_4): stw 6,0(3) bf 30,L(dus_5) lhz 7,4(4) - sth 7,4(3) + sth 7,4(3) bf 31,L(dus_0) lbz 8,6(4) stb 8,6(3) @@ -588,8 +588,8 @@ L(dus_0): bge cr0, L(du4_do) blt cr5, L(du1_do) beq cr5, L(du2_do) - b L(du3_do) - + b L(du3_do) + .align 4 L(du1_do): bf 30,L(du1_1dw) @@ -663,7 +663,7 @@ L(du1_fini): /* calculate and store the final DW */ sldi 0,6, 8 srdi 8,7, 64-8 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -740,7 +740,7 @@ L(du2_fini): /* calculate and store the final DW */ sldi 0,6, 16 srdi 8,7, 64-16 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -817,7 +817,7 @@ L(du3_fini): /* calculate and store the final DW */ sldi 0,6, 24 srdi 8,7, 64-24 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -900,7 +900,7 @@ L(du4_fini): /* calculate and store the final DW */ sldi 0,6, 32 srdi 8,7, 64-32 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -977,7 +977,7 @@ L(du5_fini): /* calculate and store the final DW */ sldi 0,6, 40 srdi 8,7, 64-40 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -1054,7 +1054,7 @@ L(du6_fini): /* calculate and store the final DW */ sldi 0,6, 48 srdi 8,7, 64-48 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -1131,10 +1131,10 @@ L(du7_fini): /* calculate and store the final DW */ sldi 0,6, 56 srdi 8,7, 64-56 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) - + .align 4 L(du_done): rldicr 0,31,0,60 @@ -1142,7 +1142,7 @@ L(du_done): beq cr1,0f /* If the tail is 0 bytes we are done! */ add 3,3,0 - add 12,12,0 + add 12,12,0 /* At this point we have a tail of 0-7 bytes and we know that the destination is double word aligned. */ 4: bf 29,2f diff --git a/sysdeps/powerpc/powerpc64/power6/wordcopy.c b/sysdeps/powerpc/powerpc64/power6/wordcopy.c index f19829c2be..751789339d 100644 --- a/sysdeps/powerpc/powerpc64/power6/wordcopy.c +++ b/sysdeps/powerpc/powerpc64/power6/wordcopy.c @@ -37,7 +37,7 @@ _wordcopy_fwd_aligned (dstp, srcp, len) if (len & 1) { ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; srcp += OPSIZ; @@ -105,10 +105,10 @@ _wordcopy_fwd_dest_aligned (dstp, srcp, len) { a1 = ((op_t *) srcp)[1]; ((op_t *) dstp)[0] = MERGE (a0, sh_1, a1, sh_2); - + if (len == 1) return; - + a0 = a1; srcp += OPSIZ; dstp += OPSIZ; @@ -137,7 +137,7 @@ _wordcopy_bwd_aligned (dstp, srcp, len) srcp -= OPSIZ; dstp -= OPSIZ; ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; len -= 1; diff --git a/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S index c09eb65c0f..d29fe9e3cd 100644 --- a/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S @@ -21,7 +21,7 @@ /* int __isnan(x) */ .machine power6 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 mftgpr r4,fp1 /* copy FPR to GPR */ lis r0,0x7ff0 diff --git a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S index bb1627fae5..67d51ada6d 100644 --- a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S +++ b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S @@ -21,7 +21,7 @@ .machine "power6" /* long long int[r3] __llrint (double x[fp1]) */ -ENTRY (__llrint) +ENTRY (__llrint) CALL_MCOUNT 0 fctid fp13,fp1 mftgpr r3,fp13 diff --git a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S index 902db67a3a..45aaceaa3e 100644 --- a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S @@ -18,13 +18,13 @@ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long long [r3] llround (float x [fp1]) - IEEE 1003.1 llround function. IEEE specifies "round to the nearest + IEEE 1003.1 llround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use Floating Convert to Integer Word with round to zero instruction. */ @@ -32,7 +32,7 @@ .machine "power6" ENTRY (__llround) CALL_MCOUNT 0 - frin fp2,fp1 /* Round to nearest +-0.5. */ + frin fp2,fp1 /* Round to nearest +-0.5. */ fctidz fp3,fp2 /* Convert To Integer DW round toward 0. */ mftgpr r3,fp3 /* Transfer integer to R3. */ blr diff --git a/sysdeps/powerpc/powerpc64/strlen.S b/sysdeps/powerpc/powerpc64/strlen.S index dafd033877..0f9b5eea9f 100644 --- a/sysdeps/powerpc/powerpc64/strlen.S +++ b/sysdeps/powerpc/powerpc64/strlen.S @@ -57,11 +57,11 @@ 2) How popular are bytes with the high bit set? If they are very rare, on some processors it might be useful to use the simpler expression ~((x - 0x01010101) | 0x7f7f7f7f) (that is, on processors with only one - ALU), but this fails when any character has its high bit set. - + ALU), but this fails when any character has its high bit set. + Answer: - 1) Added a Data Cache Block Touch early to prefetch the first 128 - byte cache line. Adding dcbt instructions to the loop would not be + 1) Added a Data Cache Block Touch early to prefetch the first 128 + byte cache line. Adding dcbt instructions to the loop would not be effective since most strings will be shorter than the cache line.*/ /* Some notes on register usage: Under the SVR4 ABI, we can use registers @@ -101,7 +101,7 @@ ENTRY (strlen) li rMASK, -1 insrdi r7F7F, r7F7F, 32, 0 /* That's the setup done, now do the first pair of doublewords. - We make an exception and use method (2) on the first two doublewords, + We make an exception and use method (2) on the first two doublewords, to reduce overhead. */ srd rMASK, rMASK, rPADN and rTMP1, r7F7F, rWORD1 diff --git a/sysdeps/powerpc/powerpc64/strncmp.S b/sysdeps/powerpc/powerpc64/strncmp.S index e2726883f2..779d9f7f6f 100644 --- a/sysdeps/powerpc/powerpc64/strncmp.S +++ b/sysdeps/powerpc/powerpc64/strncmp.S @@ -51,7 +51,7 @@ EALIGN (strncmp, 4, 0) clrldi rN, rN, 61 addi rFEFE, rFEFE, -0x101 addi r7F7F, r7F7F, 0x7f7f - cmpldi cr1, rN, 0 + cmpldi cr1, rN, 0 beq L(unaligned) mtctr rTMP /* Power4 wants mtctr 1st in dispatch group. */ @@ -62,7 +62,7 @@ EALIGN (strncmp, 4, 0) add rFEFE, rFEFE, rTMP b L(g1) -L(g0): +L(g0): ldu rWORD1, 8(rSTR1) bne- cr1, L(different) ldu rWORD2, 8(rSTR2) @@ -72,11 +72,11 @@ L(g1): add rTMP, rFEFE, rWORD1 and. rTMP, rTMP, rNEG cmpd cr1, rWORD1, rWORD2 beq+ L(g0) - + /* OK. We've hit the end of the string. We need to be careful that we don't compare two strings as different because of gunk beyond the end of the strings... */ - + L(endstring): and rTMP, r7F7F, rWORD1 beq cr1, L(equal) @@ -152,7 +152,7 @@ L(u1): lbzu rWORD1, 1(rSTR1) bne+ cr1, L(u0) -L(u2): lbzu rWORD1, -1(rSTR1) +L(u2): lbzu rWORD1, -1(rSTR1) L(u3): sub rRTN, rWORD1, rWORD2 blr END (strncmp) |