diff options
Diffstat (limited to 'sysdeps/powerpc/fpu')
| -rw-r--r-- | sysdeps/powerpc/fpu/feholdexcpt.c | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fenv_const.c | 8 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fesetenv.c | 8 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/feupdateenv.c | 6 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/s_rintf.c | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/t_sqrt.c | 2 |
6 files changed, 14 insertions, 14 deletions
diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c index 671724b287..013d2bfbb4 100644 --- a/sysdeps/powerpc/fpu/feholdexcpt.c +++ b/sysdeps/powerpc/fpu/feholdexcpt.c @@ -32,7 +32,7 @@ feholdexcept (fenv_t *envp) flag. */ new.l[1] = old.l[1] & 7; new.l[0] = old.l[0]; - + /* If the old env had any enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ diff --git a/sysdeps/powerpc/fpu/fenv_const.c b/sysdeps/powerpc/fpu/fenv_const.c index d7bb79c742..47761ebeca 100644 --- a/sysdeps/powerpc/fpu/fenv_const.c +++ b/sysdeps/powerpc/fpu/fenv_const.c @@ -16,17 +16,17 @@ License along with the GNU C Library; if not, see <http://www.gnu.org/licenses/>. */ -/* We want to specify the bit pattern of the __fe_*_env constants, so +/* We want to specify the bit pattern of the __fe_*_env constants, so pretend they're really `long long' instead of `double'. */ /* If the default argument is used we use this value. */ -const unsigned long long __fe_dfl_env __attribute__ ((aligned (8))) = +const unsigned long long __fe_dfl_env __attribute__ ((aligned (8))) = 0xfff8000000000000ULL; /* Floating-point environment where none of the exceptions are masked. */ -const unsigned long long __fe_enabled_env __attribute__ ((aligned (8))) = +const unsigned long long __fe_enabled_env __attribute__ ((aligned (8))) = 0xfff80000000000f8ULL; /* Floating-point environment with the NI bit set. */ -const unsigned long long __fe_nonieee_env __attribute__ ((aligned (8))) = +const unsigned long long __fe_nonieee_env __attribute__ ((aligned (8))) = 0xfff8000000000004ULL; diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index 953af5ddc7..e92adb4c58 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -29,21 +29,21 @@ __fesetenv (const fenv_t *envp) /* get the currently set exceptions. */ new.fenv = *envp; old.fenv = fegetenv_register (); - + /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); - + /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not + FPU to run faster because it always takes the default action and can not generate SIGFPE. */ if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); - + fesetenv_register (*envp); /* Success. */ diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c index 9faf930f36..6500ea1737 100644 --- a/sysdeps/powerpc/fpu/feupdateenv.c +++ b/sysdeps/powerpc/fpu/feupdateenv.c @@ -35,17 +35,17 @@ __feupdateenv (const fenv_t *envp) exceptions. Leave fraction rounded/inexact and FP result/CC bits unchanged. */ new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF); - + /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); - + /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not + FPU to run faster because it always takes the default action and can not generate SIGFPE. */ if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); diff --git a/sysdeps/powerpc/fpu/s_rintf.c b/sysdeps/powerpc/fpu/s_rintf.c index 7b1476780e..4a32a4343a 100644 --- a/sysdeps/powerpc/fpu/s_rintf.c +++ b/sysdeps/powerpc/fpu/s_rintf.c @@ -36,7 +36,7 @@ __rintf (float x) x = -(x - TWO23); } } - + return x; } weak_alias (__rintf, rintf) diff --git a/sysdeps/powerpc/fpu/t_sqrt.c b/sysdeps/powerpc/fpu/t_sqrt.c index c49380c0fd..9ed7436ae6 100644 --- a/sysdeps/powerpc/fpu/t_sqrt.c +++ b/sysdeps/powerpc/fpu/t_sqrt.c @@ -50,7 +50,7 @@ const float __t_sqrt[1024] = { 0.9847,0.5077, 0.9857,0.5072, 0.9867,0.5067, 0.9877,0.5062, 0.9887,0.5057, 0.9897,0.5052, 0.9907,0.5047, 0.9917,0.5042, 0.9926,0.5037, 0.9936,0.5032, 0.9946,0.5027, 0.9956,0.5022, 0.9966,0.5017, 0.9976,0.5012, 0.9985,0.5007, -0.9995,0.5002, +0.9995,0.5002, 1.0010,0.4995, 1.0029,0.4985, 1.0049,0.4976, 1.0068,0.4966, 1.0088,0.4957, 1.0107,0.4947, 1.0126,0.4938, 1.0145,0.4928, 1.0165,0.4919, 1.0184,0.4910, 1.0203,0.4901, 1.0222,0.4891, 1.0241,0.4882, 1.0260,0.4873, 1.0279,0.4864, |