diff options
Diffstat (limited to 'REORG.TODO/sysdeps/powerpc/bits')
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/endian.h | 36 | ||||
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/fenv.h | 180 | ||||
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/fenvinline.h | 79 | ||||
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/fp-fast.h | 39 | ||||
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/hwcap.h | 71 | ||||
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/link.h | 156 | ||||
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/mathinline.h | 132 | ||||
| -rw-r--r-- | REORG.TODO/sysdeps/powerpc/bits/setjmp.h | 50 |
8 files changed, 743 insertions, 0 deletions
diff --git a/REORG.TODO/sysdeps/powerpc/bits/endian.h b/REORG.TODO/sysdeps/powerpc/bits/endian.h new file mode 100644 index 0000000000..db150e9efc --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/endian.h @@ -0,0 +1,36 @@ +/* Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* PowerPC can be little or big endian. Hopefully gcc will know... */ + +#ifndef _ENDIAN_H +# error "Never use <bits/endian.h> directly; include <endian.h> instead." +#endif + +#if defined __BIG_ENDIAN__ || defined _BIG_ENDIAN +# if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN +# error Both BIG_ENDIAN and LITTLE_ENDIAN defined! +# endif +# define __BYTE_ORDER __BIG_ENDIAN +#else +# if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN +# define __BYTE_ORDER __LITTLE_ENDIAN +# else +# warning Cannot determine current byte order, assuming big-endian. +# define __BYTE_ORDER __BIG_ENDIAN +# endif +#endif diff --git a/REORG.TODO/sysdeps/powerpc/bits/fenv.h b/REORG.TODO/sysdeps/powerpc/bits/fenv.h new file mode 100644 index 0000000000..c279b484f5 --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/fenv.h @@ -0,0 +1,180 @@ +/* Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _FENV_H +# error "Never use <bits/fenv.h> directly; include <fenv.h> instead." +#endif + + +/* Define bits representing the exception. We use the bit positions of + the appropriate bits in the FPSCR... */ +enum + { + FE_INEXACT = +#define FE_INEXACT (1 << (31 - 6)) + FE_INEXACT, + FE_DIVBYZERO = +#define FE_DIVBYZERO (1 << (31 - 5)) + FE_DIVBYZERO, + FE_UNDERFLOW = +#define FE_UNDERFLOW (1 << (31 - 4)) + FE_UNDERFLOW, + FE_OVERFLOW = +#define FE_OVERFLOW (1 << (31 - 3)) + FE_OVERFLOW, + + /* ... except for FE_INVALID, for which we use bit 31. FE_INVALID + actually corresponds to bits 7 through 12 and 21 through 23 + in the FPSCR, but we can't use that because the current draft + says that it must be a power of 2. Instead we use bit 2 which + is the summary bit for all the FE_INVALID exceptions, which + kind of makes sense. */ + FE_INVALID = +#define FE_INVALID (1 << (31 - 2)) + FE_INVALID, + +#ifdef __USE_GNU + /* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an + input to a routine is equivalent to setting all of these bits; + FE_INVALID will be set on output from a routine iff one of + these bits is set. Note, though, that you can't disable or + enable these exceptions individually. */ + + /* Operation with a sNaN. */ + FE_INVALID_SNAN = +# define FE_INVALID_SNAN (1 << (31 - 7)) + FE_INVALID_SNAN, + + /* Inf - Inf */ + FE_INVALID_ISI = +# define FE_INVALID_ISI (1 << (31 - 8)) + FE_INVALID_ISI, + + /* Inf / Inf */ + FE_INVALID_IDI = +# define FE_INVALID_IDI (1 << (31 - 9)) + FE_INVALID_IDI, + + /* 0 / 0 */ + FE_INVALID_ZDZ = +# define FE_INVALID_ZDZ (1 << (31 - 10)) + FE_INVALID_ZDZ, + + /* Inf * 0 */ + FE_INVALID_IMZ = +# define FE_INVALID_IMZ (1 << (31 - 11)) + FE_INVALID_IMZ, + + /* Comparison with a NaN. */ + FE_INVALID_COMPARE = +# define FE_INVALID_COMPARE (1 << (31 - 12)) + FE_INVALID_COMPARE, + + /* Invalid operation flag for software (not set by hardware). */ + /* Note that some chips don't have this implemented, presumably + because no-one expected anyone to write software for them %-). */ + FE_INVALID_SOFTWARE = +# define FE_INVALID_SOFTWARE (1 << (31 - 21)) + FE_INVALID_SOFTWARE, + + /* Square root of negative number (including -Inf). */ + /* Note that some chips don't have this implemented. */ + FE_INVALID_SQRT = +# define FE_INVALID_SQRT (1 << (31 - 22)) + FE_INVALID_SQRT, + + /* Conversion-to-integer of a NaN or a number too large or too small. */ + FE_INVALID_INTEGER_CONVERSION = +# define FE_INVALID_INTEGER_CONVERSION (1 << (31 - 23)) + FE_INVALID_INTEGER_CONVERSION + +# define FE_ALL_INVALID \ + (FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \ + | FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \ + | FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION) +#endif + }; + +#define FE_ALL_EXCEPT \ + (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID) + +/* PowerPC chips support all of the four defined rounding modes. We + use the bit pattern in the FPSCR as the values for the + appropriate macros. */ +enum + { + FE_TONEAREST = +#define FE_TONEAREST 0 + FE_TONEAREST, + FE_TOWARDZERO = +#define FE_TOWARDZERO 1 + FE_TOWARDZERO, + FE_UPWARD = +#define FE_UPWARD 2 + FE_UPWARD, + FE_DOWNWARD = +#define FE_DOWNWARD 3 + FE_DOWNWARD + }; + +/* Type representing exception flags. */ +typedef unsigned int fexcept_t; + +/* Type representing floating-point environment. We leave it as 'double' + for efficiency reasons (rather than writing it to a 32-bit integer). */ +typedef double fenv_t; + +/* If the default argument is used we use this value. */ +extern const fenv_t __fe_dfl_env; +#define FE_DFL_ENV (&__fe_dfl_env) + +#ifdef __USE_GNU +/* Floating-point environment where all exceptions are enabled. Note that + this is not sufficient to give you SIGFPE. */ +extern const fenv_t __fe_enabled_env; +# define FE_ENABLED_ENV (&__fe_enabled_env) + +/* Floating-point environment with (processor-dependent) non-IEEE floating + point. */ +extern const fenv_t __fe_nonieee_env; +# define FE_NONIEEE_ENV (&__fe_nonieee_env) + +/* Floating-point environment with all exceptions enabled. Note that + just evaluating this value does not change the processor exception mode. + Passing this mask to fesetenv will result in a prctl syscall to change + the MSR FE0/FE1 bits to "Precise Mode". On some processors this will + result in slower floating point execution. This will last until an + fenv or exception mask is installed that disables all FP exceptions. */ +# define FE_NOMASK_ENV FE_ENABLED_ENV + +/* Floating-point environment with all exceptions disabled. Note that + just evaluating this value does not change the processor exception mode. + Passing this mask to fesetenv will result in a prctl syscall to change + the MSR FE0/FE1 bits to "Ignore Exceptions Mode". On most processors + this allows the fastest possible floating point execution.*/ +# define FE_MASK_ENV FE_DFL_ENV + +#endif + +#if __GLIBC_USE (IEC_60559_BFP_EXT) +/* Type representing floating-point control modes. */ +typedef double femode_t; + +/* Default floating-point control modes. */ +extern const femode_t __fe_dfl_mode; +# define FE_DFL_MODE (&__fe_dfl_mode) +#endif diff --git a/REORG.TODO/sysdeps/powerpc/bits/fenvinline.h b/REORG.TODO/sysdeps/powerpc/bits/fenvinline.h new file mode 100644 index 0000000000..4110bdfbbf --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/fenvinline.h @@ -0,0 +1,79 @@ +/* Inline floating-point environment handling functions for powerpc. + Copyright (C) 1995-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#if defined __GNUC__ && !defined _SOFT_FLOAT && !defined __NO_FPRS__ + +/* Inline definition for fegetround. */ +# define __fegetround() \ + (__extension__ ({ int __fegetround_result; \ + __asm__ __volatile__ \ + ("mcrfs 7,7 ; mfcr %0" \ + : "=r"(__fegetround_result) : : "cr7"); \ + __fegetround_result & 3; })) +# define fegetround() __fegetround () + +# ifndef __NO_MATH_INLINES +/* The weird 'i#*X' constraints on the following suppress a gcc + warning when __excepts is not a constant. Otherwise, they mean the + same as just plain 'i'. */ + +# if __GNUC_PREREQ(3, 4) + +/* Inline definition for feraiseexcept. */ +# define feraiseexcept(__excepts) \ + (__extension__ ({ \ + int __e = __excepts; \ + int __ret; \ + if (__builtin_constant_p (__e) \ + && (__e & (__e - 1)) == 0 \ + && __e != FE_INVALID) \ + { \ + if (__e != 0) \ + __asm__ __volatile__ ("mtfsb1 %0" \ + : : "i#*X" (__builtin_clz (__e))); \ + __ret = 0; \ + } \ + else \ + __ret = feraiseexcept (__e); \ + __ret; \ + })) + +/* Inline definition for feclearexcept. */ +# define feclearexcept(__excepts) \ + (__extension__ ({ \ + int __e = __excepts; \ + int __ret; \ + if (__builtin_constant_p (__e) \ + && (__e & (__e - 1)) == 0 \ + && __e != FE_INVALID) \ + { \ + if (__e != 0) \ + __asm__ __volatile__ ("mtfsb0 %0" \ + : : "i#*X" (__builtin_clz (__e))); \ + __ret = 0; \ + } \ + else \ + __ret = feclearexcept (__e); \ + __ret; \ + })) + +# endif /* __GNUC_PREREQ(3, 4). */ + +# endif /* !__NO_MATH_INLINES. */ + +#endif /* __GNUC__ && !_SOFT_FLOAT && !__NO_FPRS__ */ diff --git a/REORG.TODO/sysdeps/powerpc/bits/fp-fast.h b/REORG.TODO/sysdeps/powerpc/bits/fp-fast.h new file mode 100644 index 0000000000..9faf1b7c51 --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/fp-fast.h @@ -0,0 +1,39 @@ +/* Define FP_FAST_* macros. PowerPC version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _MATH_H +# error "Never use <bits/fp-fast.h> directly; include <math.h> instead." +#endif + +#ifdef __USE_ISOC99 + +/* The GCC 4.6 compiler will define __FP_FAST_FMA{,F,L} if the fma{,f,l} + builtins are supported. */ +# if (!defined _SOFT_FLOAT && !defined __NO_FPRS__) || defined __FP_FAST_FMA +# define FP_FAST_FMA 1 +# endif + +# if (!defined _SOFT_FLOAT && !defined __NO_FPRS__) || defined __FP_FAST_FMAF +# define FP_FAST_FMAF 1 +# endif + +# ifdef __FP_FAST_FMAL +# define FP_FAST_FMAL 1 +# endif + +#endif diff --git a/REORG.TODO/sysdeps/powerpc/bits/hwcap.h b/REORG.TODO/sysdeps/powerpc/bits/hwcap.h new file mode 100644 index 0000000000..c9daeedfde --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/hwcap.h @@ -0,0 +1,71 @@ +/* Defines for bits in AT_HWCAP and AT_HWCAP2. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined(_SYS_AUXV_H) && !defined(_SYSDEPS_SYSDEP_H) +# error "Never include <bits/hwcap.h> directly; use <sys/auxv.h> instead." +#endif + +/* The bit numbers must match those in the kernel's asm/cputable.h. */ + +/* Feature definitions in AT_HWCAP. */ +#define PPC_FEATURE_32 0x80000000 /* 32-bit mode. */ +#define PPC_FEATURE_64 0x40000000 /* 64-bit mode. */ +#define PPC_FEATURE_601_INSTR 0x20000000 /* 601 chip, Old POWER ISA. */ +#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 /* SIMD/Vector Unit. */ +#define PPC_FEATURE_HAS_FPU 0x08000000 /* Floating Point Unit. */ +#define PPC_FEATURE_HAS_MMU 0x04000000 /* Memory Management Unit. */ +#define PPC_FEATURE_HAS_4xxMAC 0x02000000 /* 4xx Multiply Accumulator. */ +#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 /* Unified I/D cache. */ +#define PPC_FEATURE_HAS_SPE 0x00800000 /* Signal Processing ext. */ +#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 /* SPE Float. */ +#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 /* SPE Double. */ +#define PPC_FEATURE_NO_TB 0x00100000 /* 601/403gx have no timebase */ +#define PPC_FEATURE_POWER4 0x00080000 /* POWER4 ISA 2.00 */ +#define PPC_FEATURE_POWER5 0x00040000 /* POWER5 ISA 2.02 */ +#define PPC_FEATURE_POWER5_PLUS 0x00020000 /* POWER5+ ISA 2.03 */ +#define PPC_FEATURE_CELL_BE 0x00010000 /* CELL Broadband Engine */ +#define PPC_FEATURE_BOOKE 0x00008000 /* ISA Category Embedded */ +#define PPC_FEATURE_SMT 0x00004000 /* Simultaneous + Multi-Threading */ +#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 +#define PPC_FEATURE_ARCH_2_05 0x00001000 /* ISA 2.05 */ +#define PPC_FEATURE_PA6T 0x00000800 /* PA Semi 6T Core */ +#define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal FP Unit */ +#define PPC_FEATURE_POWER6_EXT 0x00000200 /* P6 + mffgpr/mftgpr */ +#define PPC_FEATURE_ARCH_2_06 0x00000100 /* ISA 2.06 */ +#define PPC_FEATURE_HAS_VSX 0x00000080 /* P7 Vector Extension. */ +#define PPC_FEATURE_PSERIES_PERFMON_COMPAT 0x00000040 +#define PPC_FEATURE_TRUE_LE 0x00000002 +#define PPC_FEATURE_PPC_LE 0x00000001 + +/* Feature definitions in AT_HWCAP2. */ +#define PPC_FEATURE2_ARCH_2_07 0x80000000 /* ISA 2.07 */ +#define PPC_FEATURE2_HAS_HTM 0x40000000 /* Hardware Transactional + Memory */ +#define PPC_FEATURE2_HAS_DSCR 0x20000000 /* Data Stream Control + Register */ +#define PPC_FEATURE2_HAS_EBB 0x10000000 /* Event Base Branching */ +#define PPC_FEATURE2_HAS_ISEL 0x08000000 /* Integer Select */ +#define PPC_FEATURE2_HAS_TAR 0x04000000 /* Target Address Register */ +#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000 /* Target supports vector + instruction. */ +#define PPC_FEATURE2_HTM_NOSC 0x01000000 /* Kernel aborts transaction + when a syscall is made. */ +#define PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.0 */ +#define PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float + 128-bit */ diff --git a/REORG.TODO/sysdeps/powerpc/bits/link.h b/REORG.TODO/sysdeps/powerpc/bits/link.h new file mode 100644 index 0000000000..1cab121a65 --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/link.h @@ -0,0 +1,156 @@ +/* Machine-specific declarations for dynamic linker interface. PowerPC version + Copyright (C) 2004-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _LINK_H +# error "Never include <bits/link.h> directly; use <link.h> instead." +#endif + + +#if __ELF_NATIVE_CLASS == 32 + +/* Registers for entry into PLT on PPC32. */ +typedef struct La_ppc32_regs +{ + uint32_t lr_reg[8]; + double lr_fp[8]; + uint32_t lr_vreg[12][4]; + uint32_t lr_r1; + uint32_t lr_lr; +} La_ppc32_regs; + +/* Return values for calls from PLT on PPC32. */ +typedef struct La_ppc32_retval +{ + uint32_t lrv_r3; + uint32_t lrv_r4; + double lrv_fp[8]; + uint32_t lrv_v2[4]; +} La_ppc32_retval; + + +__BEGIN_DECLS + +extern Elf32_Addr la_ppc32_gnu_pltenter (Elf32_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + La_ppc32_regs *__regs, + unsigned int *__flags, + const char *__symname, + long int *__framesizep); +extern unsigned int la_ppc32_gnu_pltexit (Elf32_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + const La_ppc32_regs *__inregs, + La_ppc32_retval *__outregs, + const char *__symname); + +__END_DECLS + +#elif __ELF_NATIVE_CLASS == 64 +# if _CALL_ELF != 2 + +/* Registers for entry into PLT on PPC64. */ +typedef struct La_ppc64_regs +{ + uint64_t lr_reg[8]; + double lr_fp[13]; + uint32_t __padding; + uint32_t lr_vrsave; + uint32_t lr_vreg[12][4]; + uint64_t lr_r1; + uint64_t lr_lr; +} La_ppc64_regs; + +/* Return values for calls from PLT on PPC64. */ +typedef struct La_ppc64_retval +{ + uint64_t lrv_r3; + uint64_t lrv_r4; + double lrv_fp[4]; /* f1-f4, float - complex long double. */ + uint32_t lrv_v2[4]; /* v2. */ +} La_ppc64_retval; + + +__BEGIN_DECLS + +extern Elf64_Addr la_ppc64_gnu_pltenter (Elf64_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + La_ppc64_regs *__regs, + unsigned int *__flags, + const char *__symname, + long int *__framesizep); +extern unsigned int la_ppc64_gnu_pltexit (Elf64_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + const La_ppc64_regs *__inregs, + La_ppc64_retval *__outregs, + const char *__symname); + +__END_DECLS + +# else + +/* Registers for entry into PLT on PPC64 in the ELFv2 ABI. */ +typedef struct La_ppc64v2_regs +{ + uint64_t lr_reg[8]; + double lr_fp[13]; + uint32_t __padding; + uint32_t lr_vrsave; + uint32_t lr_vreg[12][4] __attribute__ ((aligned (16))); + uint64_t lr_r1; + uint64_t lr_lr; +} La_ppc64v2_regs; + +/* Return values for calls from PLT on PPC64 in the ELFv2 ABI. */ +typedef struct La_ppc64v2_retval +{ + uint64_t lrv_r3; + uint64_t lrv_r4; + double lrv_fp[10]; + uint32_t lrv_vreg[8][4] __attribute__ ((aligned (16))); +} La_ppc64v2_retval; + + +__BEGIN_DECLS + +extern Elf64_Addr la_ppc64v2_gnu_pltenter (Elf64_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + La_ppc64v2_regs *__regs, + unsigned int *__flags, + const char *__symname, + long int *__framesizep); +extern unsigned int la_ppc64v2_gnu_pltexit (Elf64_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + const La_ppc64v2_regs *__inregs, + La_ppc64v2_retval *__outregs, + const char *__symname); + +__END_DECLS + +# endif +#endif diff --git a/REORG.TODO/sysdeps/powerpc/bits/mathinline.h b/REORG.TODO/sysdeps/powerpc/bits/mathinline.h new file mode 100644 index 0000000000..e5f0cd30f2 --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/mathinline.h @@ -0,0 +1,132 @@ +/* Inline math functions for powerpc. + Copyright (C) 1995-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _MATH_H +# error "Never use <bits/mathinline.h> directly; include <math.h> instead." +#endif + +#ifndef __extern_inline +# define __MATH_INLINE __inline +#else +# define __MATH_INLINE __extern_inline +#endif /* __cplusplus */ + +#if defined __GNUC__ && !defined _SOFT_FLOAT && !defined __NO_FPRS__ + +#ifdef __USE_ISOC99 +# if !__GNUC_PREREQ (2,97) +# define __unordered_cmp(x, y) \ + (__extension__ \ + ({ __typeof__(x) __x = (x); __typeof__(y) __y = (y); \ + unsigned __r; \ + __asm__("fcmpu 7,%1,%2 ; mfcr %0" : "=r" (__r) : "f" (__x), "f"(__y) \ + : "cr7"); \ + __r; })) + +# undef isgreater +# undef isgreaterequal +# undef isless +# undef islessequal +# undef islessgreater +# undef isunordered + +# define isgreater(x, y) (__unordered_cmp (x, y) >> 2 & 1) +# define isgreaterequal(x, y) ((__unordered_cmp (x, y) & 6) != 0) +# define isless(x, y) (__unordered_cmp (x, y) >> 3 & 1) +# define islessequal(x, y) ((__unordered_cmp (x, y) & 0xA) != 0) +# define islessgreater(x, y) ((__unordered_cmp (x, y) & 0xC) != 0) +# define isunordered(x, y) (__unordered_cmp (x, y) & 1) + +# endif /* __GNUC_PREREQ (2,97) */ + +/* The gcc, version 2.7 or below, has problems with all this inlining + code. So disable it for this version of the compiler. */ +# if __GNUC_PREREQ (2, 8) +/* Test for negative number. Used in the signbit() macro. */ +__MATH_INLINE int +__NTH (__signbitf (float __x)) +{ +#if __GNUC_PREREQ (4, 0) + return __builtin_signbitf (__x); +#else + __extension__ union { float __f; int __i; } __u = { __f: __x }; + return __u.__i < 0; +#endif +} +__MATH_INLINE int +__NTH (__signbit (double __x)) +{ +#if __GNUC_PREREQ (4, 0) + return __builtin_signbit (__x); +#else + __extension__ union { double __d; long long __i; } __u = { __d: __x }; + return __u.__i < 0; +#endif +} +# ifdef __LONG_DOUBLE_128__ +__MATH_INLINE int +__NTH (__signbitl (long double __x)) +{ + return __signbit ((double) __x); +} +# endif +# endif +#endif /* __USE_ISOC99 */ + +#if !defined __NO_MATH_INLINES && defined __OPTIMIZE__ + +#ifdef __USE_ISOC99 + +# ifndef __powerpc64__ +__MATH_INLINE long int lrint (double __x) __THROW; +__MATH_INLINE long int +__NTH (lrint (double __x)) +{ + union { + double __d; + long long __ll; + } __u; + __asm__ ("fctiw %0,%1" : "=f"(__u.__d) : "f"(__x)); + return __u.__ll; +} + +__MATH_INLINE long int lrintf (float __x) __THROW; +__MATH_INLINE long int +__NTH (lrintf (float __x)) +{ + return lrint ((double) __x); +} +# endif + +__MATH_INLINE double fdim (double __x, double __y) __THROW; +__MATH_INLINE double +__NTH (fdim (double __x, double __y)) +{ + return __x <= __y ? 0 : __x - __y; +} + +__MATH_INLINE float fdimf (float __x, float __y) __THROW; +__MATH_INLINE float +__NTH (fdimf (float __x, float __y)) +{ + return __x <= __y ? 0 : __x - __y; +} + +#endif /* __USE_ISOC99 */ +#endif /* !__NO_MATH_INLINES && __OPTIMIZE__ */ +#endif /* __GNUC__ && !_SOFT_FLOAT && !__NO_FPRS__ */ diff --git a/REORG.TODO/sysdeps/powerpc/bits/setjmp.h b/REORG.TODO/sysdeps/powerpc/bits/setjmp.h new file mode 100644 index 0000000000..02568951e9 --- /dev/null +++ b/REORG.TODO/sysdeps/powerpc/bits/setjmp.h @@ -0,0 +1,50 @@ +/* Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* Define the machine-dependent type `jmp_buf'. PowerPC version. */ +#ifndef _BITS_SETJMP_H +#define _BITS_SETJMP_H 1 + +#if !defined _SETJMP_H && !defined _PTHREAD_H +# error "Never include <bits/setjmp.h> directly; use <setjmp.h> instead." +#endif + +/* The previous bits/setjmp.h had __jmp_buf defined as a structure. + We use an array of 'long int' instead, to make writing the + assembler easier. Naturally, user code should not depend on + either representation. */ + +#include <bits/wordsize.h> + +/* The current powerpc 32-bit Altivec ABI specifies for SVR4 ABI and EABI + the vrsave must be at byte 248 & v20 at byte 256. So we must pad this + correctly on 32 bit. It also insists that vecregs are only gauranteed + 4 byte alignment so we need to use vperm in the setjmp/longjmp routines. + We have to version the code because members like int __mask_was_saved + in the jmp_buf will move as jmp_buf is now larger than 248 bytes. We + cannot keep the altivec jmp_buf backward compatible with the jmp_buf. */ +#ifndef _ASM +# if __WORDSIZE == 64 +typedef long int __jmp_buf[64] __attribute__ ((__aligned__ (16))); +# else +/* The alignment is not essential, i.e.the buffer can be copied to a 4 byte + aligned buffer as per the ABI it is just added for performance reasons. */ +typedef long int __jmp_buf[64 + (12 * 4)] __attribute__ ((__aligned__ (16))); +# endif +#endif + +#endif /* bits/setjmp.h */ |