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| author | H.J. Lu <hongjiu.lu@intel.com> | 2009-12-13 09:47:02 -0800 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2009-12-13 09:47:02 -0800 |
| commit | 51ddd2c01e0636f713417f30379b876e85558f61 (patch) | |
| tree | 1d9762899998ee78590cf88e81be1f7a4b014370 /sysdeps/x86_64/multiarch/strcspn.S | |
| parent | 9b2f1d4b58f192445db38d5bfe5de0eff2dc3b27 (diff) | |
| download | glibc-51ddd2c01e0636f713417f30379b876e85558f61.tar.gz | |
Define bit_XXX and index_XXX.
This patch defines bit_XXX and index_XXX and use them to check processor
feature in assembly code. It can prevent typos in processor feature
check.
Diffstat (limited to 'sysdeps/x86_64/multiarch/strcspn.S')
| -rw-r--r-- | sysdeps/x86_64/multiarch/strcspn.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sysdeps/x86_64/multiarch/strcspn.S b/sysdeps/x86_64/multiarch/strcspn.S index cc75ab70e6..f00d52c2c0 100644 --- a/sysdeps/x86_64/multiarch/strcspn.S +++ b/sysdeps/x86_64/multiarch/strcspn.S @@ -23,7 +23,7 @@ #ifdef HAVE_SSE4_SUPPORT #include <sysdep.h> -#include <ifunc-defines.h> +#include <init-arch.h> #ifdef USE_AS_STRPBRK #define STRCSPN_SSE42 __strpbrk_sse42 @@ -49,7 +49,7 @@ ENTRY(STRCSPN) jne 1f call __init_cpu_features 1: leaq STRCSPN_SSE2(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq STRCSPN_SSE42(%rip), %rax 2: ret |