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| author | Ulrich Drepper <drepper@redhat.com> | 2009-05-31 17:52:05 -0700 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2009-05-31 17:52:05 -0700 |
| commit | 963cb6fcb47ca212c0c57cc57bd7510f6549579c (patch) | |
| tree | e0b12d2f0af3a97193aaa12a7162e6c38b828a4f /sysdeps/x86_64/cacheinfo.c | |
| parent | fd469aac31dc09f1328c8c4b976f887ebd592c56 (diff) | |
| download | glibc-963cb6fcb47ca212c0c57cc57bd7510f6549579c.tar.gz | |
Simplify CPUID value handling.
SO far Intel and AMD use exactly the same bits meaning the same
things in CPUID index 1. Simplify the code. Should an architecture
come along which doesn't use the same semantics then it must use a
different index value than COMMON_CPUID_INDEX_1.
Diffstat (limited to 'sysdeps/x86_64/cacheinfo.c')
| -rw-r--r-- | sysdeps/x86_64/cacheinfo.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index cd192caad8..362687c181 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -489,10 +489,10 @@ init_cacheinfo (void) } #ifdef USE_MULTIARCH - eax = __cpu_features.cpuid[INTEL_CPUID_INDEX_1].eax; - ebx = __cpu_features.cpuid[INTEL_CPUID_INDEX_1].ebx; - ecx = __cpu_features.cpuid[INTEL_CPUID_INDEX_1].ecx; - edx = __cpu_features.cpuid[INTEL_CPUID_INDEX_1].edx; + eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax; + ebx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx; + ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx; + edx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].edx; #else asm volatile ("cpuid" : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) |