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| author | Ulrich Drepper <drepper@redhat.com> | 2009-07-23 13:42:46 -0700 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2009-07-23 13:42:46 -0700 |
| commit | 3e9099b4f6666cd05b62d2829f65161daddb151b (patch) | |
| tree | 91be21d2342e432272c8f5429f3ae7eb2a76fbfa /sysdeps/x86_64/cacheinfo.c | |
| parent | d28797e426aa7e4e380a7ae10faf4aa3c4767e0b (diff) | |
| download | glibc-3e9099b4f6666cd05b62d2829f65161daddb151b.tar.gz | |
Add more cache descriptors for L3 caches on x86 and x86-64.
The most recent AP 485 describes a few more cache descriptors for
L3 caches with 24-way associativity.
Diffstat (limited to 'sysdeps/x86_64/cacheinfo.c')
| -rw-r--r-- | sysdeps/x86_64/cacheinfo.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index 362687c181..07939099b9 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -100,6 +100,9 @@ static const struct intel_02_cache_info { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 }, { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 }, { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 }, + { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 }, + { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 }, + { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 }, }; #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known [0])) |