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author | H.J. Lu <hjl.tools@gmail.com> | 2017-06-20 08:33:29 -0700 |
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committer | H.J. Lu <hjl.tools@gmail.com> | 2017-06-20 08:37:28 -0700 |
commit | 905947c30455bea5eed42cdffd771a11b1554f1d (patch) | |
tree | ce9e6f9c47f9d1f5536a68fbd3244ed26a6d2387 /sysdeps/x86/cacheinfo.c | |
parent | beb52f502f0477465313675d2a0fbf3962e130b8 (diff) | |
download | glibc-905947c30455bea5eed42cdffd771a11b1554f1d.tar.gz |
tunables: Add IFUNC selection and cache sizes
The current IFUNC selection is based on microbenchmarks in glibc. It
should give the best performance for most workloads. But other choices
may have better performance for a particular workload or on the hardware
which wasn't available at the selection was made. The environment
variable, GLIBC_TUNABLES=glibc.tune.ifunc=-xxx,yyy,-zzz...., can be used
to enable CPU/ARCH feature yyy, disable CPU/ARCH feature yyy and zzz,
where the feature name is case-sensitive and has to match the ones in
cpu-features.h. It can be used by glibc developers to override the
IFUNC selection to tune for a new processor or improve performance for
a particular workload. It isn't intended for normal end users.
NOTE: the IFUNC selection may change over time. Please check all
multiarch implementations when experimenting.
Also, GLIBC_TUNABLES=glibc.tune.x86_non_temporal_threshold=NUMBER is
provided to set threshold to use non temporal store to NUMBER,
GLIBC_TUNABLES=glibc.tune.x86_data_cache_size=NUMBER to set data cache
size, GLIBC_TUNABLES=glibc.tune.x86_shared_cache_size=NUMBER to set
shared cache size.
* elf/dl-tunables.list (tune): Add ifunc,
x86_non_temporal_threshold,
x86_data_cache_size and x86_shared_cache_size.
* manual/tunables.texi: Document glibc.tune.ifunc,
glibc.tune.x86_data_cache_size, glibc.tune.x86_shared_cache_size
and glibc.tune.x86_non_temporal_threshold.
* sysdeps/unix/sysv/linux/x86/dl-sysdep.c: New file.
* sysdeps/x86/cpu-tunables.c: Likewise.
* sysdeps/x86/cacheinfo.c
(init_cacheinfo): Check and get data cache size, shared cache
size and non temporal threshold from cpu_features.
* sysdeps/x86/cpu-features.c [HAVE_TUNABLES] (TUNABLE_NAMESPACE):
New.
[HAVE_TUNABLES] Include <unistd.h>.
[HAVE_TUNABLES] Include <elf/dl-tunables.h>.
[HAVE_TUNABLES] (TUNABLE_CALLBACK (set_ifunc)): Likewise.
[HAVE_TUNABLES] (init_cpu_features): Use TUNABLE_GET to set
IFUNC selection, data cache size, shared cache size and non
temporal threshold.
* sysdeps/x86/cpu-features.h (cpu_features): Add data_cache_size,
shared_cache_size and non_temporal_threshold.
Diffstat (limited to 'sysdeps/x86/cacheinfo.c')
-rw-r--r-- | sysdeps/x86/cacheinfo.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 8000fd1e99..9542dfba80 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -752,6 +752,9 @@ intel_bug_no_cache_info: #endif } + if (cpu_features->data_cache_size != 0) + data = cpu_features->data_cache_size; + if (data > 0) { __x86_raw_data_cache_size_half = data / 2; @@ -762,6 +765,9 @@ intel_bug_no_cache_info: __x86_data_cache_size = data; } + if (cpu_features->shared_cache_size != 0) + shared = cpu_features->shared_cache_size; + if (shared > 0) { __x86_raw_shared_cache_size_half = shared / 2; @@ -777,7 +783,9 @@ intel_bug_no_cache_info: store becomes faster on a 8-core processor. This is the 3/4 of the total shared cache size. */ __x86_shared_non_temporal_threshold - = __x86_shared_cache_size * threads * 3 / 4; + = (cpu_features->non_temporal_threshold != 0 + ? cpu_features->non_temporal_threshold + : __x86_shared_cache_size * threads * 3 / 4); } #endif |