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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-11-25 14:32:54 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-11-26 07:06:28 -0500 |
| commit | 704f794714704ba430d84d10d6809acaf7ca59bf (patch) | |
| tree | 753816581f7d1f54d4af4921d776077b31a9a4e4 /sysdeps/powerpc/powerpc64/bits/atomic.h | |
| parent | cdcb42d7f786fe5ee1ca60065924d0b5c6649dd0 (diff) | |
| download | glibc-704f794714704ba430d84d10d6809acaf7ca59bf.tar.gz | |
powerpc: Fix missing barriers in atomic_exchange_and_add_{acq,rel}
On powerpc, atomic_exchange_and_add is implemented without any
barriers. This patchs adds the missing instruction and memory barrier
for acquire and release semanthics.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/bits/atomic.h')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/bits/atomic.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/sysdeps/powerpc/powerpc64/bits/atomic.h b/sysdeps/powerpc/powerpc64/bits/atomic.h index 83b5dfebbd..46117b0200 100644 --- a/sysdeps/powerpc/powerpc64/bits/atomic.h +++ b/sysdeps/powerpc/powerpc64/bits/atomic.h @@ -186,6 +186,34 @@ __val; \ }) +#define __arch_atomic_exchange_and_add_64_acq(mem, value) \ + ({ \ + __typeof (*mem) __val, __tmp; \ + __asm __volatile ("1: ldarx %0,0,%3" MUTEX_HINT_ACQ "\n" \ + " add %1,%0,%4\n" \ + " stdcx. %1,0,%3\n" \ + " bne- 1b\n" \ + __ARCH_ACQ_INSTR \ + : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ + : "b" (mem), "r" (value), "m" (*mem) \ + : "cr0", "memory"); \ + __val; \ + }) + +#define __arch_atomic_exchange_and_add_64_rel(mem, value) \ + ({ \ + __typeof (*mem) __val, __tmp; \ + __asm __volatile (__ARCH_REL_INSTR "\n" \ + "1: ldarx %0,0,%3" MUTEX_HINT_REL "\n" \ + " add %1,%0,%4\n" \ + " stdcx. %1,0,%3\n" \ + " bne- 1b" \ + : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ + : "b" (mem), "r" (value), "m" (*mem) \ + : "cr0", "memory"); \ + __val; \ + }) + #define __arch_atomic_increment_val_64(mem) \ ({ \ __typeof (*(mem)) __val; \ |