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authorRyan S. Arnold <rsa@us.ibm.com>2009-06-16 08:29:04 -0700
committerUlrich Drepper <drepper@redhat.com>2009-06-16 08:29:04 -0700
commit25bfbb9e0e610afaf6b67e5ee1a1a5338018c42e (patch)
tree17ec2d068a4539085dd40f4fdc50255424a20be5 /sysdeps/powerpc/powerpc32/power6/memset.S
parentb23964c6207124341b89cefc316dc512a669c17b (diff)
downloadglibc-25bfbb9e0e610afaf6b67e5ee1a1a5338018c42e.tar.gz
Fix incorrect use of cmpldi in 32-bit PPC code.
The 32-bit PowerPC POWER6 memcpy uses the cmpldi insn when it should use a cmplwi. BZ #10107
Diffstat (limited to 'sysdeps/powerpc/powerpc32/power6/memset.S')
-rw-r--r--sysdeps/powerpc/powerpc32/power6/memset.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/sysdeps/powerpc/powerpc32/power6/memset.S b/sysdeps/powerpc/powerpc32/power6/memset.S
index 10fb7b9786..cc65b7be9a 100644
--- a/sysdeps/powerpc/powerpc32/power6/memset.S
+++ b/sysdeps/powerpc/powerpc32/power6/memset.S
@@ -1,5 +1,5 @@
/* Optimized 32-bit memset implementation for POWER6.
- Copyright (C) 1997,99, 2000,02,03,06,2007 Free Software Foundation, Inc.
+ Copyright (C) 1997,99,2000,02,03,06,2007,2009 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -240,7 +240,7 @@ L(nzCacheAligned256):
cmplwi cr1,rLEN,256
addi rMEMP3,rMEMP,64
#ifdef NOT_IN_libc
-/* When we are not in libc we should use only GPRs to avoid the FPU lock
+/* When we are not in libc we should use only GPRs to avoid the FPU lock
interrupt. */
stw rCHR,0(rMEMP)
stw rCHR,4(rMEMP)
@@ -381,7 +381,7 @@ L(cacheAligned):
blt cr1,L(cacheAligned1)
li rMEMP2,128
L(cacheAlignedx):
- cmpldi cr5,rLEN,640
+ cmplwi cr5,rLEN,640
blt cr6,L(cacheAligned128)
bgt cr5,L(cacheAligned512)
cmplwi cr6,rLEN,512