diff options
| author | Torvald Riegel <triegel@redhat.com> | 2016-06-14 15:12:00 +0200 |
|---|---|---|
| committer | Torvald Riegel <triegel@redhat.com> | 2016-06-24 23:04:40 +0300 |
| commit | 76a0b73e8102c5bfb5cb791e34992472f5d1d33e (patch) | |
| tree | 2fcd8ece66b944eed3ca046d79651c7a7573736f /sysdeps/powerpc/powerpc32/atomic-machine.h | |
| parent | 40244be3729149ff440caf18e445ec17b0d0b511 (diff) | |
| download | glibc-76a0b73e8102c5bfb5cb791e34992472f5d1d33e.tar.gz | |
Remove atomic_compare_and_exchange_bool_rel.
atomic_compare_and_exchange_bool_rel and
catomic_compare_and_exchange_bool_rel are removed and replaced with the
new C11-like atomic_compare_exchange_weak_release. The concurrent code
in nscd/cache.c has not been reviewed yet, so this patch does not add
detailed comments.
* nscd/cache.c (cache_add): Use new C11-like atomic operation instead
of atomic_compare_and_exchange_bool_rel.
* nptl/pthread_mutex_unlock.c (__pthread_mutex_unlock_full): Likewise.
* include/atomic.h (atomic_compare_and_exchange_bool_rel,
catomic_compare_and_exchange_bool_rel): Remove.
* sysdeps/aarch64/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/alpha/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/arm/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/mips/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/tile/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
Diffstat (limited to 'sysdeps/powerpc/powerpc32/atomic-machine.h')
| -rw-r--r-- | sysdeps/powerpc/powerpc32/atomic-machine.h | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h index 1d407b3490..40a8b7b966 100644 --- a/sysdeps/powerpc/powerpc32/atomic-machine.h +++ b/sysdeps/powerpc/powerpc32/atomic-machine.h @@ -58,22 +58,6 @@ __tmp != 0; \ }) -#define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \ -({ \ - unsigned int __tmp; \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: lwarx %0,0,%1" MUTEX_HINT_REL "\n" \ - " subf. %0,%2,%0\n" \ - " bne 2f\n" \ - " stwcx. %3,0,%1\n" \ - " bne- 1b\n" \ - "2: " \ - : "=&r" (__tmp) \ - : "b" (mem), "r" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp != 0; \ -}) - /* Powerpc32 processors don't implement the 64-bit (doubleword) forms of load and reserve (ldarx) and store conditional (stdcx.) instructions. So for powerpc32 we stub out the 64-bit forms. */ @@ -83,9 +67,6 @@ #define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ (abort (), (__typeof (*mem)) 0) -#define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \ - (abort (), 0) - #define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \ (abort (), (__typeof (*mem)) 0) |