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| author | Wilco Dijkstra <Wilco.Dijkstra@arm.com> | 2018-12-19 18:28:24 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2019-09-06 18:49:02 +0100 |
| commit | 1533274d5fd6eec6fd5972bc2f5c643261349c17 (patch) | |
| tree | 4e075af832887a4aca3e24c81977d4a5fa317e18 /sysdeps/aarch64/multiarch | |
| parent | 57922433fa038faa6e37798b9655f85a94978d89 (diff) | |
| download | glibc-1533274d5fd6eec6fd5972bc2f5c643261349c17.tar.gz | |
[AArch64] Add ifunc support for Ares
Add Ares to the midr_el0 list and support ifunc dispatch. Since Ares
supports 2 128-bit loads/stores, use Neon registers for memcpy by
selecting __memcpy_falkor by default (we should rename this to
__memcpy_simd or similar).
* manual/tunables.texi (glibc.cpu.name): Add ares tunable.
* sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
__memcpy_falkor for ares.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
Add new define.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
Add ares cpu.
(cherry picked from commit 02f440c1ef5d5d79552a524065aa3e2fabe469b9)
Diffstat (limited to 'sysdeps/aarch64/multiarch')
| -rw-r--r-- | sysdeps/aarch64/multiarch/memcpy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/aarch64/multiarch/memcpy.c b/sysdeps/aarch64/multiarch/memcpy.c index 4a04a63b0f..8f5d4e7df5 100644 --- a/sysdeps/aarch64/multiarch/memcpy.c +++ b/sysdeps/aarch64/multiarch/memcpy.c @@ -36,7 +36,7 @@ extern __typeof (__redirect_memcpy) __memcpy_falkor attribute_hidden; libc_ifunc (__libc_memcpy, (IS_THUNDERX (midr) ? __memcpy_thunderx - : (IS_FALKOR (midr) || IS_PHECDA (midr) + : (IS_FALKOR (midr) || IS_PHECDA (midr) || IS_ARES (midr) ? __memcpy_falkor : (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr) ? __memcpy_thunderx2 |