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| author | Jose E. Marchesi <jose.marchesi@oracle.com> | 2017-10-20 20:29:06 -0200 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2017-12-11 18:36:54 -0200 |
| commit | ef915cebe6e7e0ce83242d1261df2419feb3a9cc (patch) | |
| tree | f764cc35f38c2392f97080f700a1300840a29866 /mach/lock-intern.h | |
| parent | 20f015e10c74ab17fae92b4f579f09b5db342be7 (diff) | |
| download | glibc-ef915cebe6e7e0ce83242d1261df2419feb3a9cc.tar.gz | |
sparc: M7 optimized memset/bzeroazanella/ifunc-c-sparc-m7
Tested in sparcv9-*-* and sparc64-*-* targets in both multi and
non-multi arch configurations.
Support added to identify Sparc M7/T7/S7/M8/T8 processor capability.
Usual "make check" correctness tests run with no regressions.
Performance tests run on Sparc S7 using new code and old niagara4 code.
Optimizations for memset also apply to bzero as they share code.
For memset/bzero, performance comparison with niagara4 code:
For memset nonzero data,
256-1023 bytes - 60-90% gain (in cache); 5% gain (out of cache)
1K+ bytes - 80-260% gain (in cache); 40-80% gain (out of cache)
For memset zero data (and bzero),
256-1023 bytes - 80-120% gain (in cache), 0% gain (out of cache)
1024+ bytes - 2-4x gain (in cache), 10-35% gain (out of cache)
Jose E. Marchesi <jose.marchesi@oracle.com>
Adhemerval Zanella <adhemerval.zanella@linaro.org>
* sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile
(sysdeps_routines): Add memset-niagara7.
* sysdeps/sparc/sparc64/multiarch/Makefile (sysdes_rotuines):
Likewise.
* sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara7.S: New
file.
* sysdeps/sparc/sparc64/multiarch/memset-niagara7.S: Likewise.
* sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c
(__libc_ifunc_impl_list): Add __bzero_niagara7 and __memset_niagara7.
* sysdeps/sparc/sparc64/multiarch/ifunc-memset.h (IFUNC_SELECTOR):
Add niagara7 option.
Diffstat (limited to 'mach/lock-intern.h')
0 files changed, 0 insertions, 0 deletions