Prepare for radical source tree reorganization.zack/build-layout-experiment

All top-level files and directories are moved into a temporary storage
directory, REORG.TODO, except for files that will certainly still
exist in their current form at top level when we're done (COPYING,
COPYING.LIB, LICENSES, NEWS, README), all old ChangeLog files (which
are moved to the new directory OldChangeLogs, instead), and the
generated file INSTALL (which is just deleted; in the new order, there
will be no generated files checked into version control).

14 files changed, 2144 insertions, 0 deletions

diff --git a/REORG.TODO/sysdeps/x86/fpu/Makefile b/REORG.TODO/sysdeps/x86/fpu/Makefile
new file mode 100644
index 0000000000..a8047a4504
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/Makefile
@@ -0,0 +1,11 @@
+ifeq ($(subdir),math)
+libm-support += powl_helper
+tests += test-fenv-sse test-fenv-clear-sse test-fenv-x87 test-fenv-sse-2 \
+	 test-flt-eval-method-387 test-flt-eval-method-sse
+CFLAGS-test-fenv-sse.c += -msse2 -mfpmath=sse
+CFLAGS-test-fenv-clear-sse.c += -msse2 -mfpmath=sse
+CFLAGS-test-fenv-sse-2.c += -msse2 -mfpmath=sse
+CFLAGS-test-flt-eval-method-387.c += -fexcess-precision=standard -mfpmath=387
+CFLAGS-test-flt-eval-method-sse.c += -fexcess-precision=standard -msse2 \
+				     -mfpmath=sse
+endif
diff --git a/REORG.TODO/sysdeps/x86/fpu/bits/fenv.h b/REORG.TODO/sysdeps/x86/fpu/bits/fenv.h
new file mode 100644
index 0000000000..fd7327902c
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/bits/fenv.h
@@ -0,0 +1,168 @@
+/* Copyright (C) 1997-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _FENV_H
+# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
+#endif
+
+/* Define bits representing the exception.  We use the bit positions
+   of the appropriate bits in the FPU control word.  */
+enum
+  {
+    FE_INVALID =
+#define FE_INVALID	0x01
+      FE_INVALID,
+    __FE_DENORM = 0x02,
+    FE_DIVBYZERO =
+#define FE_DIVBYZERO	0x04
+      FE_DIVBYZERO,
+    FE_OVERFLOW =
+#define FE_OVERFLOW	0x08
+      FE_OVERFLOW,
+    FE_UNDERFLOW =
+#define FE_UNDERFLOW	0x10
+      FE_UNDERFLOW,
+    FE_INEXACT =
+#define FE_INEXACT	0x20
+      FE_INEXACT
+  };
+
+#define FE_ALL_EXCEPT \
+	(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
+
+/* The ix87 FPU supports all of the four defined rounding modes.  We
+   use again the bit positions in the FPU control word as the values
+   for the appropriate macros.  */
+enum
+  {
+    FE_TONEAREST =
+#define FE_TONEAREST	0
+      FE_TONEAREST,
+    FE_DOWNWARD =
+#define FE_DOWNWARD	0x400
+      FE_DOWNWARD,
+    FE_UPWARD =
+#define FE_UPWARD	0x800
+      FE_UPWARD,
+    FE_TOWARDZERO =
+#define FE_TOWARDZERO	0xc00
+      FE_TOWARDZERO
+  };
+
+
+/* Type representing exception flags.  */
+typedef unsigned short int fexcept_t;
+
+
+/* Type representing floating-point environment.  This structure
+   corresponds to the layout of the block written by the `fstenv'
+   instruction and has additional fields for the contents of the MXCSR
+   register as written by the `stmxcsr' instruction.  */
+typedef struct
+  {
+    unsigned short int __control_word;
+    unsigned short int __glibc_reserved1;
+    unsigned short int __status_word;
+    unsigned short int __glibc_reserved2;
+    unsigned short int __tags;
+    unsigned short int __glibc_reserved3;
+    unsigned int __eip;
+    unsigned short int __cs_selector;
+    unsigned int __opcode:11;
+    unsigned int __glibc_reserved4:5;
+    unsigned int __data_offset;
+    unsigned short int __data_selector;
+    unsigned short int __glibc_reserved5;
+#ifdef __x86_64__
+    unsigned int __mxcsr;
+#endif
+  }
+fenv_t;
+
+/* If the default argument is used we use this value.  */
+#define FE_DFL_ENV	((const fenv_t *) -1)
+
+#ifdef __USE_GNU
+/* Floating-point environment where none of the exception is masked.  */
+# define FE_NOMASK_ENV	((const fenv_t *) -2)
+#endif
+
+#if __GLIBC_USE (IEC_60559_BFP_EXT)
+/* Type representing floating-point control modes.  */
+typedef struct
+  {
+    unsigned short int __control_word;
+    unsigned short int __glibc_reserved;
+    unsigned int __mxcsr;
+  }
+femode_t;
+
+/* Default floating-point control modes.  */
+# define FE_DFL_MODE	((const femode_t *) -1L)
+#endif
+
+
+#ifdef __USE_EXTERN_INLINES
+__BEGIN_DECLS
+
+/* Optimized versions.  */
+extern int __REDIRECT_NTH (__feraiseexcept_renamed, (int), feraiseexcept);
+__extern_always_inline void
+__NTH (__feraiseexcept_invalid_divbyzero (int __excepts))
+{
+  if ((FE_INVALID & __excepts) != 0)
+    {
+      /* One example of an invalid operation is 0.0 / 0.0.  */
+      float __f = 0.0;
+
+# ifdef __SSE_MATH__
+      __asm__ __volatile__ ("divss %0, %0 " : : "x" (__f));
+# else
+      __asm__ __volatile__ ("fdiv %%st, %%st(0); fwait"
+			    : "=t" (__f) : "0" (__f));
+# endif
+      (void) &__f;
+    }
+  if ((FE_DIVBYZERO & __excepts) != 0)
+    {
+      float __f = 1.0;
+      float __g = 0.0;
+
+# ifdef __SSE_MATH__
+      __asm__ __volatile__ ("divss %1, %0" : : "x" (__f), "x" (__g));
+# else
+      __asm__ __volatile__ ("fdivp %%st, %%st(1); fwait"
+			    : "=t" (__f) : "0" (__f), "u" (__g) : "st(1)");
+# endif
+      (void) &__f;
+    }
+}
+__extern_inline int
+__NTH (feraiseexcept (int __excepts))
+{
+  if (__builtin_constant_p (__excepts)
+      && (__excepts & ~(FE_INVALID | FE_DIVBYZERO)) == 0)
+    {
+      __feraiseexcept_invalid_divbyzero (__excepts);
+      return 0;
+    }
+
+  return __feraiseexcept_renamed (__excepts);
+}
+
+__END_DECLS
+#endif
diff --git a/REORG.TODO/sysdeps/x86/fpu/bits/math-vector.h b/REORG.TODO/sysdeps/x86/fpu/bits/math-vector.h
new file mode 100644
index 0000000000..419af076a7
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/bits/math-vector.h
@@ -0,0 +1,63 @@
+/* Platform-specific SIMD declarations of math functions.
+   Copyright (C) 2014-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _MATH_H
+# error "Never include <bits/math-vector.h> directly;\
+ include <math.h> instead."
+#endif
+
+/* Get default empty definitions for simd declarations.  */
+#include <bits/libm-simd-decl-stubs.h>
+
+#if defined __x86_64__ && defined __FAST_MATH__
+# if defined _OPENMP && _OPENMP >= 201307
+/* OpenMP case.  */
+#  define __DECL_SIMD_x86_64 _Pragma ("omp declare simd notinbranch")
+# elif __GNUC_PREREQ (6,0)
+/* W/o OpenMP use GCC 6.* __attribute__ ((__simd__)).  */
+#  define __DECL_SIMD_x86_64 __attribute__ ((__simd__ ("notinbranch")))
+# endif
+
+# ifdef __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_cos
+#  define __DECL_SIMD_cos __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_cosf
+#  define __DECL_SIMD_cosf __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_sin
+#  define __DECL_SIMD_sin __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_sinf
+#  define __DECL_SIMD_sinf __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_sincos
+#  define __DECL_SIMD_sincos __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_sincosf
+#  define __DECL_SIMD_sincosf __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_log
+#  define __DECL_SIMD_log __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_logf
+#  define __DECL_SIMD_logf __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_exp
+#  define __DECL_SIMD_exp __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_expf
+#  define __DECL_SIMD_expf __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_pow
+#  define __DECL_SIMD_pow __DECL_SIMD_x86_64
+#  undef __DECL_SIMD_powf
+#  define __DECL_SIMD_powf __DECL_SIMD_x86_64
+
+# endif
+#endif
diff --git a/REORG.TODO/sysdeps/x86/fpu/bits/mathinline.h b/REORG.TODO/sysdeps/x86/fpu/bits/mathinline.h
new file mode 100644
index 0000000000..bcd99bdf74
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/bits/mathinline.h
@@ -0,0 +1,962 @@
+/* Inline math functions for i387 and SSE.
+   Copyright (C) 1995-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _MATH_H
+# error "Never use <bits/mathinline.h> directly; include <math.h> instead."
+#endif
+
+#ifndef __extern_always_inline
+# define __MATH_INLINE __inline
+#else
+# define __MATH_INLINE __extern_always_inline
+#endif
+
+
+#if defined __USE_ISOC99 && defined __GNUC__ && __GNUC__ >= 2
+/* GCC 2.97 and up have builtins that actually can be used.  */
+# if !__GNUC_PREREQ (2,97)
+/* ISO C99 defines some macros to perform unordered comparisons.  The
+   ix87 FPU supports this with special opcodes and we should use them.
+   These must not be inline functions since we have to be able to handle
+   all floating-point types.  */
+#  undef isgreater
+#  undef isgreaterequal
+#  undef isless
+#  undef islessequal
+#  undef islessgreater
+#  undef isunordered
+#  ifdef __i686__
+/* For the PentiumPro and more recent processors we can provide
+   better code.  */
+#   define isgreater(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucomip %%st(1), %%st; seta %%al"			      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st");	      \
+	__result; })
+#   define isgreaterequal(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucomip %%st(1), %%st; setae %%al"			      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st");	      \
+	__result; })
+
+#   define isless(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucomip %%st(1), %%st; seta %%al"			      \
+		 : "=a" (__result) : "u" (x), "t" (y) : "cc", "st");	      \
+	__result; })
+
+#   define islessequal(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucomip %%st(1), %%st; setae %%al"			      \
+		 : "=a" (__result) : "u" (x), "t" (y) : "cc", "st");	      \
+	__result; })
+
+#   define islessgreater(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucomip %%st(1), %%st; setne %%al"			      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st");	      \
+	__result; })
+
+#   define isunordered(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucomip %%st(1), %%st; setp %%al"			      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st");	      \
+	__result; })
+#  else
+/* This is the dumb, portable code for i386 and above.  */
+#   define isgreater(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucompp; fnstsw; testb $0x45, %%ah; setz %%al"	      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st", "st(1)"); \
+	__result; })
+
+#   define isgreaterequal(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucompp; fnstsw; testb $0x05, %%ah; setz %%al"	      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st", "st(1)"); \
+	__result; })
+
+#   define isless(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucompp; fnstsw; testb $0x45, %%ah; setz %%al"	      \
+		 : "=a" (__result) : "u" (x), "t" (y) : "cc", "st", "st(1)"); \
+	__result; })
+
+#   define islessequal(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucompp; fnstsw; testb $0x05, %%ah; setz %%al"	      \
+		 : "=a" (__result) : "u" (x), "t" (y) : "cc", "st", "st(1)"); \
+	__result; })
+
+#   define islessgreater(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucompp; fnstsw; testb $0x44, %%ah; setz %%al"	      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st", "st(1)"); \
+	__result; })
+
+#   define isunordered(x, y) \
+     ({ register char __result;						      \
+	__asm__ ("fucompp; fnstsw; sahf; setp %%al"			      \
+		 : "=a" (__result) : "u" (y), "t" (x) : "cc", "st", "st(1)"); \
+	__result; })
+#  endif /* __i686__ */
+# endif	/* GCC 2.97 */
+
+/* The gcc, version 2.7 or below, has problems with all this inlining
+   code.  So disable it for this version of the compiler.  */
+# if __GNUC_PREREQ (2, 8)
+
+/* Test for negative number.  Used in the signbit() macro.  */
+__MATH_INLINE int
+__NTH (__signbitf (float __x))
+{
+#  ifdef __SSE2_MATH__
+  int __m;
+  __asm ("pmovmskb %1, %0" : "=r" (__m) : "x" (__x));
+  return (__m & 0x8) != 0;
+#  else
+  __extension__ union { float __f; int __i; } __u = { __f: __x };
+  return __u.__i < 0;
+#  endif
+}
+__MATH_INLINE int
+__NTH (__signbit (double __x))
+{
+#  ifdef __SSE2_MATH__
+  int __m;
+  __asm ("pmovmskb %1, %0" : "=r" (__m) : "x" (__x));
+  return (__m & 0x80) != 0;
+#  else
+  __extension__ union { double __d; int __i[2]; } __u = { __d: __x };
+  return __u.__i[1] < 0;
+#  endif
+}
+__MATH_INLINE int
+__NTH (__signbitl (long double __x))
+{
+  __extension__ union { long double __l; int __i[3]; } __u = { __l: __x };
+  return (__u.__i[2] & 0x8000) != 0;
+}
+
+# endif
+#endif
+
+
+/* The gcc, version 2.7 or below, has problems with all this inlining
+   code.  So disable it for this version of the compiler.  */
+#if __GNUC_PREREQ (2, 8)
+# if !__GNUC_PREREQ (3, 4) && !defined __NO_MATH_INLINES \
+     && defined __OPTIMIZE__
+/* GCC 3.4 introduced builtins for all functions below, so
+   there's no need to define any of these inline functions.  */
+
+#  ifdef __USE_ISOC99
+
+/* Round to nearest integer.  */
+#   ifdef __SSE_MATH__
+__MATH_INLINE long int
+__NTH (lrintf (float __x))
+{
+  long int __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("cvtss2si %1, %0" : "=r" (__res) : "xm" (__x));
+  return __res;
+}
+#   endif
+#   ifdef __SSE2_MATH__
+__MATH_INLINE long int
+__NTH (lrint (double __x))
+{
+  long int __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("cvtsd2si %1, %0" : "=r" (__res) : "xm" (__x));
+  return __res;
+}
+#   endif
+#   ifdef __x86_64__
+__extension__
+__MATH_INLINE long long int
+__NTH (llrintf (float __x))
+{
+  long long int __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("cvtss2si %1, %0" : "=r" (__res) : "xm" (__x));
+  return __res;
+}
+__extension__
+__MATH_INLINE long long int
+__NTH (llrint (double __x))
+{
+  long long int __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("cvtsd2si %1, %0" : "=r" (__res) : "xm" (__x));
+  return __res;
+}
+#   endif
+
+#   if defined __FINITE_MATH_ONLY__ && __FINITE_MATH_ONLY__ > 0 \
+       && defined __SSE2_MATH__
+/* Determine maximum of two values.  */
+__MATH_INLINE float
+__NTH (fmaxf (float __x, float __y))
+{
+#    ifdef __AVX__
+  float __res;
+  __asm ("vmaxss %2, %1, %0" : "=x" (__res) : "x" (x), "xm" (__y));
+  return __res;
+#    else
+  __asm ("maxss %1, %0" : "+x" (__x) : "xm" (__y));
+  return __x;
+#    endif
+}
+__MATH_INLINE double
+__NTH (fmax (double __x, double __y))
+{
+#    ifdef __AVX__
+  float __res;
+  __asm ("vmaxsd %2, %1, %0" : "=x" (__res) : "x" (x), "xm" (__y));
+  return __res;
+#    else
+  __asm ("maxsd %1, %0" : "+x" (__x) : "xm" (__y));
+  return __x;
+#    endif
+}
+
+/* Determine minimum of two values.  */
+__MATH_INLINE float
+__NTH (fminf (float __x, float __y))
+{
+#    ifdef __AVX__
+  float __res;
+  __asm ("vminss %2, %1, %0" : "=x" (__res) : "x" (x), "xm" (__y));
+  return __res;
+#    else
+  __asm ("minss %1, %0" : "+x" (__x) : "xm" (__y));
+  return __x;
+#    endif
+}
+__MATH_INLINE double
+__NTH (fmin (double __x, double __y))
+{
+#    ifdef __AVX__
+  float __res;
+  __asm ("vminsd %2, %1, %0" : "=x" (__res) : "x" (x), "xm" (__y));
+  return __res;
+#    else
+  __asm ("minsd %1, %0" : "+x" (__x) : "xm" (__y));
+  return __x;
+#    endif
+}
+#   endif
+
+#  endif
+
+#  if defined __SSE4_1__ && defined __SSE2_MATH__
+#   if defined __USE_XOPEN_EXTENDED || defined __USE_ISOC99
+
+/* Round to nearest integer.  */
+__MATH_INLINE double
+__NTH (rint (double __x))
+{
+  double __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("roundsd $4, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+__MATH_INLINE float
+__NTH (rintf (float __x))
+{
+  float __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("roundss $4, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+
+#    ifdef __USE_ISOC99
+/* Round to nearest integer without raising inexact exception.  */
+__MATH_INLINE double
+__NTH (nearbyint (double __x))
+{
+  double __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("roundsd $0xc, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+__MATH_INLINE float
+__NTH (nearbyintf (float __x))
+{
+  float __res;
+  /* Mark as volatile since the result is dependent on the state of
+     the SSE control register (the rounding mode).  Otherwise GCC might
+     remove these assembler instructions since it does not know about
+     the rounding mode change and cannot currently be told.  */
+  __asm __volatile__ ("roundss $0xc, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+#    endif
+
+#   endif
+
+/* Smallest integral value not less than X.  */
+__MATH_INLINE double
+__NTH (ceil (double __x))
+{
+  double __res;
+  __asm ("roundsd $2, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+
+__MATH_INLINE float
+__NTH (ceilf (float __x))
+{
+  float __res;
+  __asm ("roundss $2, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+
+/* Largest integer not greater than X.  */
+__MATH_INLINE double
+__NTH (floor (double __x))
+{
+  double __res;
+  __asm ("roundsd $1, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+
+__MATH_INLINE float
+__NTH (floorf (float __x))
+{
+  float __res;
+  __asm ("roundss $1, %1, %0" : "=x" (__res) : "xm" (__x));
+  return __res;
+}
+#  endif
+# endif
+#endif
+
+/* Disable x87 inlines when -fpmath=sse is passed and also when we're building
+   on x86_64.  Older gcc (gcc-3.2 for example) does not define __SSE2_MATH__
+   for x86_64.  */
+#if !defined __SSE2_MATH__ && !defined __x86_64__
+# if ((!defined __NO_MATH_INLINES || defined __LIBC_INTERNAL_MATH_INLINES) \
+     && defined __OPTIMIZE__)
+
+/* The inline functions do not set errno or raise necessarily the
+   correct exceptions.  */
+#  undef math_errhandling
+
+/* A macro to define float, double, and long double versions of various
+   math functions for the ix87 FPU.  FUNC is the function name (which will
+   be suffixed with f and l for the float and long double version,
+   respectively).  OP is the name of the FPU operation.
+   We define two sets of macros.  The set with the additional NP
+   doesn't add a prototype declaration.  */
+
+#  ifdef __USE_ISOC99
+#   define __inline_mathop(func, op) \
+  __inline_mathop_ (double, func, op)					      \
+  __inline_mathop_ (float, __CONCAT(func,f), op)			      \
+  __inline_mathop_ (long double, __CONCAT(func,l), op)
+#   define __inline_mathopNP(func, op) \
+  __inline_mathopNP_ (double, func, op)					      \
+  __inline_mathopNP_ (float, __CONCAT(func,f), op)			      \
+  __inline_mathopNP_ (long double, __CONCAT(func,l), op)
+#  else
+#   define __inline_mathop(func, op) \
+  __inline_mathop_ (double, func, op)
+#   define __inline_mathopNP(func, op) \
+  __inline_mathopNP_ (double, func, op)
+#  endif
+
+#  define __inline_mathop_(float_type, func, op) \
+  __inline_mathop_decl_ (float_type, func, op, "0" (__x))
+#  define __inline_mathopNP_(float_type, func, op) \
+  __inline_mathop_declNP_ (float_type, func, op, "0" (__x))
+
+
+#  ifdef __USE_ISOC99
+#   define __inline_mathop_decl(func, op, params...) \
+  __inline_mathop_decl_ (double, func, op, params)			      \
+  __inline_mathop_decl_ (float, __CONCAT(func,f), op, params)		      \
+  __inline_mathop_decl_ (long double, __CONCAT(func,l), op, params)
+#   define __inline_mathop_declNP(func, op, params...) \
+  __inline_mathop_declNP_ (double, func, op, params)			      \
+  __inline_mathop_declNP_ (float, __CONCAT(func,f), op, params)		      \
+  __inline_mathop_declNP_ (long double, __CONCAT(func,l), op, params)
+#  else
+#   define __inline_mathop_decl(func, op, params...) \
+  __inline_mathop_decl_ (double, func, op, params)
+#   define __inline_mathop_declNP(func, op, params...) \
+  __inline_mathop_declNP_ (double, func, op, params)
+#  endif
+
+#  define __inline_mathop_decl_(float_type, func, op, params...) \
+  __MATH_INLINE float_type func (float_type) __THROW;			      \
+  __inline_mathop_declNP_ (float_type, func, op, params)
+
+#  define __inline_mathop_declNP_(float_type, func, op, params...) \
+  __MATH_INLINE float_type __NTH (func (float_type __x))		      \
+  {									      \
+    register float_type __result;					      \
+    __asm __volatile__ (op : "=t" (__result) : params);			      \
+    return __result;							      \
+  }
+
+
+#  ifdef __USE_ISOC99
+#   define __inline_mathcode(func, arg, code) \
+  __inline_mathcode_ (double, func, arg, code)				      \
+  __inline_mathcode_ (float, __CONCAT(func,f), arg, code)		      \
+  __inline_mathcode_ (long double, __CONCAT(func,l), arg, code)
+#   define __inline_mathcodeNP(func, arg, code) \
+  __inline_mathcodeNP_ (double, func, arg, code)			      \
+  __inline_mathcodeNP_ (float, __CONCAT(func,f), arg, code)		      \
+  __inline_mathcodeNP_ (long double, __CONCAT(func,l), arg, code)
+#   define __inline_mathcode2(func, arg1, arg2, code) \
+  __inline_mathcode2_ (double, func, arg1, arg2, code)			      \
+  __inline_mathcode2_ (float, __CONCAT(func,f), arg1, arg2, code)	      \
+  __inline_mathcode2_ (long double, __CONCAT(func,l), arg1, arg2, code)
+#   define __inline_mathcodeNP2(func, arg1, arg2, code) \
+  __inline_mathcodeNP2_ (double, func, arg1, arg2, code)		      \
+  __inline_mathcodeNP2_ (float, __CONCAT(func,f), arg1, arg2, code)	      \
+  __inline_mathcodeNP2_ (long double, __CONCAT(func,l), arg1, arg2, code)
+#   define __inline_mathcode3(func, arg1, arg2, arg3, code) \
+  __inline_mathcode3_ (double, func, arg1, arg2, arg3, code)		      \
+  __inline_mathcode3_ (float, __CONCAT(func,f), arg1, arg2, arg3, code)	      \
+  __inline_mathcode3_ (long double, __CONCAT(func,l), arg1, arg2, arg3, code)
+#   define __inline_mathcodeNP3(func, arg1, arg2, arg3, code) \
+  __inline_mathcodeNP3_ (double, func, arg1, arg2, arg3, code)		      \
+  __inline_mathcodeNP3_ (float, __CONCAT(func,f), arg1, arg2, arg3, code)     \
+  __inline_mathcodeNP3_ (long double, __CONCAT(func,l), arg1, arg2, arg3, code)
+#  else
+#   define __inline_mathcode(func, arg, code) \
+  __inline_mathcode_ (double, func, (arg), code)
+#   define __inline_mathcodeNP(func, arg, code) \
+  __inline_mathcodeNP_ (double, func, (arg), code)
+#   define __inline_mathcode2(func, arg1, arg2, code) \
+  __inline_mathcode2_ (double, func, arg1, arg2, code)
+#   define __inline_mathcodeNP2(func, arg1, arg2, code) \
+  __inline_mathcodeNP2_ (double, func, arg1, arg2, code)
+#   define __inline_mathcode3(func, arg1, arg2, arg3, code) \
+  __inline_mathcode3_ (double, func, arg1, arg2, arg3, code)
+#   define __inline_mathcodeNP3(func, arg1, arg2, arg3, code) \
+  __inline_mathcodeNP3_ (double, func, arg1, arg2, arg3, code)
+#  endif
+
+#  define __inline_mathcode_(float_type, func, arg, code) \
+  __MATH_INLINE float_type func (float_type) __THROW;			      \
+  __inline_mathcodeNP_(float_type, func, arg, code)
+
+#  define __inline_mathcodeNP_(float_type, func, arg, code) \
+  __MATH_INLINE float_type __NTH (func (float_type arg))		      \
+  {									      \
+    code;								      \
+  }
+
+
+#  define __inline_mathcode2_(float_type, func, arg1, arg2, code) \
+  __MATH_INLINE float_type func (float_type, float_type) __THROW;	      \
+  __inline_mathcodeNP2_ (float_type, func, arg1, arg2, code)
+
+#  define __inline_mathcodeNP2_(float_type, func, arg1, arg2, code) \
+  __MATH_INLINE float_type __NTH (func (float_type arg1, float_type arg2))    \
+  {									      \
+    code;								      \
+  }
+
+#  define __inline_mathcode3_(float_type, func, arg1, arg2, arg3, code) \
+  __MATH_INLINE float_type func (float_type, float_type, float_type) __THROW; \
+  __inline_mathcodeNP3_(float_type, func, arg1, arg2, arg3, code)
+
+#  define __inline_mathcodeNP3_(float_type, func, arg1, arg2, arg3, code) \
+  __MATH_INLINE float_type __NTH (func (float_type arg1, float_type arg2,     \
+					float_type arg3))		      \
+  {									      \
+    code;								      \
+  }
+# endif
+
+
+# if !defined __NO_MATH_INLINES && defined __OPTIMIZE__
+/* Miscellaneous functions  */
+
+/* __FAST_MATH__ is defined by gcc -ffast-math.  */
+#  ifdef __FAST_MATH__
+#   ifdef __USE_GNU
+#    define __sincos_code \
+  register long double __cosr;						      \
+  register long double __sinr;						      \
+  register unsigned int __swtmp;					      \
+  __asm __volatile__							      \
+    ("fsincos\n\t"							      \
+     "fnstsw	%w2\n\t"						      \
+     "testl	$0x400, %2\n\t"						      \
+     "jz	1f\n\t"							      \
+     "fldpi\n\t"							      \
+     "fadd	%%st(0)\n\t"						      \
+     "fxch	%%st(1)\n\t"						      \
+     "2: fprem1\n\t"							      \
+     "fnstsw	%w2\n\t"						      \
+     "testl	$0x400, %2\n\t"						      \
+     "jnz	2b\n\t"							      \
+     "fstp	%%st(1)\n\t"						      \
+     "fsincos\n\t"							      \
+     "1:"								      \
+     : "=t" (__cosr), "=u" (__sinr), "=a" (__swtmp) : "0" (__x));	      \
+  *__sinx = __sinr;							      \
+  *__cosx = __cosr
+
+__MATH_INLINE void
+__NTH (__sincos (double __x, double *__sinx, double *__cosx))
+{
+  __sincos_code;
+}
+
+__MATH_INLINE void
+__NTH (__sincosf (float __x, float *__sinx, float *__cosx))
+{
+  __sincos_code;
+}
+
+__MATH_INLINE void
+__NTH (__sincosl (long double __x, long double *__sinx, long double *__cosx))
+{
+  __sincos_code;
+}
+#   endif
+
+
+/* Optimized inline implementation, sometimes with reduced precision
+   and/or argument range.  */
+
+#   if __GNUC_PREREQ (3, 5)
+#    define __expm1_code \
+  register long double __temp;						      \
+  __temp = __builtin_expm1l (__x);					      \
+  return __temp ? __temp : __x
+#   else
+#    define __expm1_code \
+  register long double __value;						      \
+  register long double __exponent;					      \
+  register long double __temp;						      \
+  __asm __volatile__							      \
+    ("fldl2e			# e^x - 1 = 2^(x * log2(e)) - 1\n\t"	      \
+     "fmul	%%st(1)		# x * log2(e)\n\t"			      \
+     "fst	%%st(1)\n\t"						      \
+     "frndint			# int(x * log2(e))\n\t"			      \
+     "fxch\n\t"								      \
+     "fsub	%%st(1)		# fract(x * log2(e))\n\t"		      \
+     "f2xm1			# 2^(fract(x * log2(e))) - 1\n\t"	      \
+     "fscale			# 2^(x * log2(e)) - 2^(int(x * log2(e)))\n\t" \
+     : "=t" (__value), "=u" (__exponent) : "0" (__x));			      \
+  __asm __volatile__							      \
+    ("fscale			# 2^int(x * log2(e))\n\t"		      \
+     : "=t" (__temp) : "0" (1.0), "u" (__exponent));			      \
+  __temp -= 1.0;							      \
+  __temp += __value;							      \
+  return __temp ? __temp : __x
+#   endif
+__inline_mathcodeNP_ (long double, __expm1l, __x, __expm1_code)
+
+#   if __GNUC_PREREQ (3, 4)
+__inline_mathcodeNP_ (long double, __expl, __x, return __builtin_expl (__x))
+#   else
+#    define __exp_code \
+  register long double __value;						      \
+  register long double __exponent;					      \
+  __asm __volatile__							      \
+    ("fldl2e			# e^x = 2^(x * log2(e))\n\t"		      \
+     "fmul	%%st(1)		# x * log2(e)\n\t"			      \
+     "fst	%%st(1)\n\t"						      \
+     "frndint			# int(x * log2(e))\n\t"			      \
+     "fxch\n\t"								      \
+     "fsub	%%st(1)		# fract(x * log2(e))\n\t"		      \
+     "f2xm1			# 2^(fract(x * log2(e))) - 1\n\t"	      \
+     : "=t" (__value), "=u" (__exponent) : "0" (__x));			      \
+  __value += 1.0;							      \
+  __asm __volatile__							      \
+    ("fscale"								      \
+     : "=t" (__value) : "0" (__value), "u" (__exponent));		      \
+  return __value
+__inline_mathcodeNP (exp, __x, __exp_code)
+__inline_mathcodeNP_ (long double, __expl, __x, __exp_code)
+#   endif
+
+
+#   if !__GNUC_PREREQ (3, 5)
+__inline_mathcodeNP (tan, __x, \
+  register long double __value;						      \
+  register long double __value2 __attribute__ ((__unused__));		      \
+  __asm __volatile__							      \
+    ("fptan"								      \
+     : "=t" (__value2), "=u" (__value) : "0" (__x));			      \
+  return __value)
+#   endif
+#  endif /* __FAST_MATH__ */
+
+
+#  if __GNUC_PREREQ (3, 4)
+__inline_mathcodeNP2_ (long double, __atan2l, __y, __x,
+		       return __builtin_atan2l (__y, __x))
+#  else
+#   define __atan2_code \
+  register long double __value;						      \
+  __asm __volatile__							      \
+    ("fpatan"								      \
+     : "=t" (__value) : "0" (__x), "u" (__y) : "st(1)");		      \
+  return __value
+#   ifdef __FAST_MATH__
+__inline_mathcodeNP2 (atan2, __y, __x, __atan2_code)
+#   endif
+__inline_mathcodeNP2_ (long double, __atan2l, __y, __x, __atan2_code)
+#  endif
+
+
+#  if defined __FAST_MATH__ && !__GNUC_PREREQ (3, 5)
+__inline_mathcodeNP2 (fmod, __x, __y, \
+  register long double __value;						      \
+  __asm __volatile__							      \
+    ("1:	fprem\n\t"						      \
+     "fnstsw	%%ax\n\t"						      \
+     "sahf\n\t"								      \
+     "jp	1b"							      \
+     : "=t" (__value) : "0" (__x), "u" (__y) : "ax", "cc");		      \
+  return __value)
+#  endif
+
+
+#  ifdef __FAST_MATH__
+#   if !__GNUC_PREREQ (3,3)
+__inline_mathopNP (sqrt, "fsqrt")
+__inline_mathopNP_ (long double, __sqrtl, "fsqrt")
+#    define __libc_sqrtl(n) __sqrtl (n)
+#   else
+#    define __libc_sqrtl(n) __builtin_sqrtl (n)
+#   endif
+#  endif
+
+#  if __GNUC_PREREQ (2, 8)
+__inline_mathcodeNP_ (double, fabs, __x, return __builtin_fabs (__x))
+#   ifdef __USE_ISOC99
+__inline_mathcodeNP_ (float, fabsf, __x, return __builtin_fabsf (__x))
+__inline_mathcodeNP_ (long double, fabsl, __x, return __builtin_fabsl (__x))
+#   endif
+__inline_mathcodeNP_ (long double, __fabsl, __x, return __builtin_fabsl (__x))
+#  else
+__inline_mathop (fabs, "fabs")
+__inline_mathop_ (long double, __fabsl, "fabs")
+# endif
+
+#  ifdef __FAST_MATH__
+#   if !__GNUC_PREREQ (3, 4)
+/* The argument range of this inline version is reduced.  */
+__inline_mathopNP (sin, "fsin")
+/* The argument range of this inline version is reduced.  */
+__inline_mathopNP (cos, "fcos")
+
+__inline_mathop_declNP (log, "fldln2; fxch; fyl2x", "0" (__x) : "st(1)")
+#   endif
+
+#   if !__GNUC_PREREQ (3, 5)
+__inline_mathop_declNP (log10, "fldlg2; fxch; fyl2x", "0" (__x) : "st(1)")
+
+__inline_mathcodeNP (asin, __x, return __atan2l (__x, __libc_sqrtl (1.0 - __x * __x)))
+__inline_mathcodeNP (acos, __x, return __atan2l (__libc_sqrtl (1.0 - __x * __x), __x))
+#   endif
+
+#   if !__GNUC_PREREQ (3, 4)
+__inline_mathop_declNP (atan, "fld1; fpatan", "0" (__x) : "st(1)")
+#   endif
+#  endif /* __FAST_MATH__ */
+
+__inline_mathcode_ (long double, __sgn1l, __x, \
+  __extension__ union { long double __xld; unsigned int __xi[3]; } __n =      \
+    { __xld: __x };							      \
+  __n.__xi[2] = (__n.__xi[2] & 0x8000) | 0x3fff;			      \
+  __n.__xi[1] = 0x80000000;						      \
+  __n.__xi[0] = 0;							      \
+  return __n.__xld)
+
+
+#  ifdef __FAST_MATH__
+/* The argument range of the inline version of sinhl is slightly reduced.  */
+__inline_mathcodeNP (sinh, __x, \
+  register long double __exm1 = __expm1l (__fabsl (__x));		      \
+  return 0.5 * (__exm1 / (__exm1 + 1.0) + __exm1) * __sgn1l (__x))
+
+__inline_mathcodeNP (cosh, __x, \
+  register long double __ex = __expl (__x);				      \
+  return 0.5 * (__ex + 1.0 / __ex))
+
+__inline_mathcodeNP (tanh, __x, \
+  register long double __exm1 = __expm1l (-__fabsl (__x + __x));	      \
+  return __exm1 / (__exm1 + 2.0) * __sgn1l (-__x))
+#  endif
+
+__inline_mathcodeNP (floor, __x, \
+  register long double __value;						      \
+  register int __ignore;						      \
+  unsigned short int __cw;						      \
+  unsigned short int __cwtmp;						      \
+  __asm __volatile ("fnstcw %3\n\t"					      \
+		    "movzwl %3, %1\n\t"					      \
+		    "andl $0xf3ff, %1\n\t"				      \
+		    "orl $0x0400, %1\n\t"	/* rounding down */	      \
+		    "movw %w1, %2\n\t"					      \
+		    "fldcw %2\n\t"					      \
+		    "frndint\n\t"					      \
+		    "fldcw %3"						      \
+		    : "=t" (__value), "=&q" (__ignore), "=m" (__cwtmp),	      \
+		      "=m" (__cw)					      \
+		    : "0" (__x));					      \
+  return __value)
+
+__inline_mathcodeNP (ceil, __x, \
+  register long double __value;						      \
+  register int __ignore;						      \
+  unsigned short int __cw;						      \
+  unsigned short int __cwtmp;						      \
+  __asm __volatile ("fnstcw %3\n\t"					      \
+		    "movzwl %3, %1\n\t"					      \
+		    "andl $0xf3ff, %1\n\t"				      \
+		    "orl $0x0800, %1\n\t"	/* rounding up */	      \
+		    "movw %w1, %2\n\t"					      \
+		    "fldcw %2\n\t"					      \
+		    "frndint\n\t"					      \
+		    "fldcw %3"						      \
+		    : "=t" (__value), "=&q" (__ignore), "=m" (__cwtmp),	      \
+		      "=m" (__cw)					      \
+		    : "0" (__x));					      \
+  return __value)
+
+#  ifdef __FAST_MATH__
+#   define __ldexp_code \
+  register long double __value;						      \
+  __asm __volatile__							      \
+    ("fscale"								      \
+     : "=t" (__value) : "0" (__x), "u" ((long double) __y));		      \
+  return __value
+
+__MATH_INLINE double
+__NTH (ldexp (double __x, int __y))
+{
+  __ldexp_code;
+}
+#  endif
+
+
+/* Optimized versions for some non-standardized functions.  */
+#  ifdef __USE_ISOC99
+
+#   ifdef __FAST_MATH__
+__inline_mathcodeNP (expm1, __x, __expm1_code)
+
+/* We cannot rely on M_SQRT being defined.  So we do it for ourself
+   here.  */
+#    define __M_SQRT2	1.41421356237309504880L	/* sqrt(2) */
+
+#    if !__GNUC_PREREQ (3, 5)
+__inline_mathcodeNP (log1p, __x, \
+  register long double __value;						      \
+  if (__fabsl (__x) >= 1.0 - 0.5 * __M_SQRT2)				      \
+    __value = logl (1.0 + __x);						      \
+  else									      \
+    __asm __volatile__							      \
+      ("fldln2\n\t"							      \
+       "fxch\n\t"							      \
+       "fyl2xp1"							      \
+       : "=t" (__value) : "0" (__x) : "st(1)");				      \
+  return __value)
+#    endif
+
+
+/* The argument range of the inline version of asinhl is slightly reduced.  */
+__inline_mathcodeNP (asinh, __x, \
+  register long double  __y = __fabsl (__x);				      \
+  return (log1pl (__y * __y / (__libc_sqrtl (__y * __y + 1.0) + 1.0) + __y)   \
+	  * __sgn1l (__x)))
+
+__inline_mathcodeNP (acosh, __x, \
+  return logl (__x + __libc_sqrtl (__x - 1.0) * __libc_sqrtl (__x + 1.0)))
+
+__inline_mathcodeNP (atanh, __x, \
+  register long double __y = __fabsl (__x);				      \
+  return -0.5 * log1pl (-(__y + __y) / (1.0 + __y)) * __sgn1l (__x))
+
+/* The argument range of the inline version of hypotl is slightly reduced.  */
+__inline_mathcodeNP2 (hypot, __x, __y,
+		      return __libc_sqrtl (__x * __x + __y * __y))
+
+#    if !__GNUC_PREREQ (3, 5)
+__inline_mathcodeNP(logb, __x, \
+  register long double __value;						      \
+  register long double __junk;						      \
+  __asm __volatile__							      \
+    ("fxtract\n\t"							      \
+     : "=t" (__junk), "=u" (__value) : "0" (__x));			      \
+  return __value)
+#    endif
+
+#   endif
+#  endif
+
+#  ifdef __USE_ISOC99
+#   ifdef __FAST_MATH__
+
+#    if !__GNUC_PREREQ (3, 5)
+__inline_mathop_declNP (log2, "fld1; fxch; fyl2x", "0" (__x) : "st(1)")
+#    endif
+
+__MATH_INLINE float
+__NTH (ldexpf (float __x, int __y))
+{
+  __ldexp_code;
+}
+
+__MATH_INLINE long double
+__NTH (ldexpl (long double __x, int __y))
+{
+  __ldexp_code;
+}
+
+__inline_mathopNP (rint, "frndint")
+#   endif /* __FAST_MATH__ */
+
+#   define __lrint_code \
+  long int __lrintres;							      \
+  __asm__ __volatile__							      \
+    ("fistpl %0"							      \
+     : "=m" (__lrintres) : "t" (__x) : "st");				      \
+  return __lrintres
+__MATH_INLINE long int
+__NTH (lrintf (float __x))
+{
+  __lrint_code;
+}
+__MATH_INLINE long int
+__NTH (lrint (double __x))
+{
+  __lrint_code;
+}
+__MATH_INLINE long int
+__NTH (lrintl (long double __x))
+{
+  __lrint_code;
+}
+#   undef __lrint_code
+
+#   define __llrint_code \
+  long long int __llrintres;						      \
+  __asm__ __volatile__							      \
+    ("fistpll %0"							      \
+     : "=m" (__llrintres) : "t" (__x) : "st");				      \
+  return __llrintres
+__extension__
+__MATH_INLINE long long int
+__NTH (llrintf (float __x))
+{
+  __llrint_code;
+}
+__extension__
+__MATH_INLINE long long int
+__NTH (llrint (double __x))
+{
+  __llrint_code;
+}
+__extension__
+__MATH_INLINE long long int
+__NTH (llrintl (long double __x))
+{
+  __llrint_code;
+}
+#   undef __llrint_code
+
+# endif
+
+
+#  ifdef __USE_MISC
+
+#   if defined __FAST_MATH__ && !__GNUC_PREREQ (3, 5)
+__inline_mathcodeNP2 (drem, __x, __y, \
+  register double __value;						      \
+  register int __clobbered;						      \
+  __asm __volatile__							      \
+    ("1:	fprem1\n\t"						      \
+     "fstsw	%%ax\n\t"						      \
+     "sahf\n\t"								      \
+     "jp	1b"							      \
+     : "=t" (__value), "=&a" (__clobbered) : "0" (__x), "u" (__y) : "cc");    \
+  return __value)
+#  endif
+
+
+/* This function is used in the `isfinite' macro.  */
+__MATH_INLINE int
+__NTH (__finite (double __x))
+{
+  return (__extension__
+	  (((((union { double __d; int __i[2]; }) {__d: __x}).__i[1]
+	     | 0x800fffffu) + 1) >> 31));
+}
+
+#  endif /* __USE_MISC  */
+
+/* Undefine some of the large macros which are not used anymore.  */
+#  undef __atan2_code
+#  ifdef __FAST_MATH__
+#   undef __expm1_code
+#   undef __exp_code
+#   undef __sincos_code
+#  endif /* __FAST_MATH__ */
+
+# endif /* __NO_MATH_INLINES  */
+
+
+/* This code is used internally in the GNU libc.  */
+# ifdef __LIBC_INTERNAL_MATH_INLINES
+__inline_mathop (__ieee754_sqrt, "fsqrt")
+__inline_mathcode2_ (long double, __ieee754_atan2l, __y, __x,
+		     register long double __value;
+		     __asm __volatile__ ("fpatan\n\t"
+					 : "=t" (__value)
+					 : "0" (__x), "u" (__y) : "st(1)");
+		     return __value;)
+# endif
+
+#endif /* !__SSE2_MATH__ && !__x86_64__ */
diff --git a/REORG.TODO/sysdeps/x86/fpu/fix-fp-int-compare-invalid.h b/REORG.TODO/sysdeps/x86/fpu/fix-fp-int-compare-invalid.h
new file mode 100644
index 0000000000..bda247d51f
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/fix-fp-int-compare-invalid.h
@@ -0,0 +1,28 @@
+/* Fix for missing "invalid" exceptions from floating-point
+   comparisons.  x86 version.
+   Copyright (C) 2016-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef FIX_FP_INT_COMPARE_INVALID_H
+#define FIX_FP_INT_COMPARE_INVALID_H	1
+
+/* As of GCC 5, both x87 and SSE comparisons use unordered comparison
+   instructions when they should use ordered comparisons
+   <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52451>.  */
+#define FIX_COMPARE_INVALID 1
+
+#endif /* fix-fp-int-compare-invalid.h */
diff --git a/REORG.TODO/sysdeps/x86/fpu/include/bits/fenv.h b/REORG.TODO/sysdeps/x86/fpu/include/bits/fenv.h
new file mode 100644
index 0000000000..a39b6fa85d
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/include/bits/fenv.h
@@ -0,0 +1,48 @@
+/* Wrapper for x86 bits/fenv.h for use when building glibc.
+   Copyright (C) 1997-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _BITS_FENV_H
+#include_next <bits/fenv.h>
+
+# ifndef _ISOMAC
+
+/* Ensure __feraiseexcept calls in glibc are optimized the same as
+   feraiseexcept calls.  */
+
+#ifdef __USE_EXTERN_INLINES
+__BEGIN_DECLS
+
+extern int __REDIRECT_NTH (____feraiseexcept_renamed, (int), __feraiseexcept);
+__extern_inline int
+__NTH (__feraiseexcept (int __excepts))
+{
+  if (__builtin_constant_p (__excepts)
+      && (__excepts & ~(FE_INVALID | FE_DIVBYZERO)) == 0)
+    {
+      __feraiseexcept_invalid_divbyzero (__excepts);
+      return 0;
+    }
+
+  return ____feraiseexcept_renamed (__excepts);
+}
+
+__END_DECLS
+#endif
+
+# endif /* _ISOMAC */
+#endif /* bits/fenv.h */
diff --git a/REORG.TODO/sysdeps/x86/fpu/powl_helper.c b/REORG.TODO/sysdeps/x86/fpu/powl_helper.c
new file mode 100644
index 0000000000..46f8cd9318
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/powl_helper.c
@@ -0,0 +1,236 @@
+/* Implement powl for x86 using extra-precision log.
+   Copyright (C) 2012-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <math.h>
+#include <math_private.h>
+#include <stdbool.h>
+
+/* High parts and low parts of -log (k/16), for integer k from 12 to
+   24.  */
+
+static const long double powl_log_table[] =
+  {
+    0x4.9a58844d36e49e1p-4L, -0x1.0522624fd558f574p-68L,
+    0x3.527da7915b3c6de4p-4L, 0x1.7d4ef4b901b99b9ep-68L,
+    0x2.22f1d044fc8f7bc8p-4L, -0x1.8e97c071a42fc388p-68L,
+    0x1.08598b59e3a0688ap-4L, 0x3.fd9bf503372c12fcp-72L,
+    -0x0p+0L, 0x0p+0L,
+    -0xf.85186008b15330cp-8L, 0x1.9b47488a6687672cp-72L,
+    -0x1.e27076e2af2e5e9ep-4L, -0xa.87ffe1fe9e155dcp-72L,
+    -0x2.bfe60e14f27a791p-4L, 0x1.83bebf1bdb88a032p-68L,
+    -0x3.91fef8f353443584p-4L, -0xb.b03de5ff734495cp-72L,
+    -0x4.59d72aeae98380e8p-4L, 0xc.e0aa3be4747dc1p-72L,
+    -0x5.1862f08717b09f4p-4L, -0x2.decdeccf1cd10578p-68L,
+    -0x5.ce75fdaef401a738p-4L, -0x9.314feb4fbde5aaep-72L,
+    -0x6.7cc8fb2fe612fcbp-4L, 0x2.5ca2642feb779f98p-68L,
+  };
+
+/* High 32 bits of log2 (e), and remainder rounded to 64 bits.  */
+static const long double log2e_hi = 0x1.71547652p+0L;
+static const long double log2e_lo = 0xb.82fe1777d0ffda1p-36L;
+
+/* Given a number with high part HI and low part LO, add the number X
+   to it and store the result in *RHI and *RLO.  It is given that
+   either |X| < |0.7 * HI|, or HI == LO == 0, and that the values are
+   small enough that no overflow occurs.  The result does not need to
+   be exact to 128 bits; 78-bit accuracy of the final accumulated
+   result suffices.  */
+
+static inline void
+acc_split (long double *rhi, long double *rlo, long double hi, long double lo,
+	   long double x)
+{
+  long double thi = hi + x;
+  long double tlo = (hi - thi) + x + lo;
+  *rhi = thi + tlo;
+  *rlo = (thi - *rhi) + tlo;
+}
+
+extern long double __powl_helper (long double x, long double y);
+libm_hidden_proto (__powl_helper)
+
+/* Given X a value that is finite and nonzero, or a NaN, and Y a
+   finite nonzero value with 0x1p-79 <= |Y| <= 0x1p78, compute X to
+   the power Y.  */
+
+long double
+__powl_helper (long double x, long double y)
+{
+  if (isnan (x))
+    return __ieee754_expl (y * __ieee754_logl (x));
+  bool negate;
+  if (x < 0)
+    {
+      long double absy = fabsl (y);
+      if (absy >= 0x1p64L)
+	negate = false;
+      else
+	{
+	  unsigned long long yll = absy;
+	  if (yll != absy)
+	    return __ieee754_expl (y * __ieee754_logl (x));
+	  negate = (yll & 1) != 0;
+	}
+      x = fabsl (x);
+    }
+  else
+    negate = false;
+
+  /* We need to compute Y * log2 (X) to at least 64 bits after the
+     point for normal results (that is, to at least 78 bits
+     precision).  */
+  int x_int_exponent;
+  long double x_frac;
+  x_frac = __frexpl (x, &x_int_exponent);
+  if (x_frac <= 0x0.aaaaaaaaaaaaaaaap0L) /* 2.0L / 3.0L, rounded down */
+    {
+      x_frac *= 2.0;
+      x_int_exponent--;
+    }
+
+  long double log_x_frac_hi, log_x_frac_lo;
+  /* Determine an initial approximation to log (X_FRAC) using
+     POWL_LOG_TABLE, and multiply by a value K/16 to reduce to an
+     interval (24/25, 26/25).  */
+  int k = (int) ((16.0L / x_frac) + 0.5L);
+  log_x_frac_hi = powl_log_table[2 * k - 24];
+  log_x_frac_lo = powl_log_table[2 * k - 23];
+  long double x_frac_low;
+  if (k == 16)
+    x_frac_low = 0.0L;
+  else
+    {
+      /* Mask off low 5 bits of X_FRAC so the multiplication by K/16
+	 is exact.  These bits are small enough that they can be
+	 corrected for by adding log2 (e) * X_FRAC_LOW to the final
+	 result.  */
+      int32_t se;
+      u_int32_t i0, i1;
+      GET_LDOUBLE_WORDS (se, i0, i1, x_frac);
+      x_frac_low = x_frac;
+      i1 &= 0xffffffe0;
+      SET_LDOUBLE_WORDS (x_frac, se, i0, i1);
+      x_frac_low -= x_frac;
+      x_frac_low /= x_frac;
+      x_frac *= k / 16.0L;
+    }
+
+  /* Now compute log (X_FRAC) for X_FRAC in (24/25, 26/25).  Separate
+     W = X_FRAC - 1 into high 16 bits and remaining bits, so that
+     multiplications for low-order power series terms are exact.  The
+     remaining bits are small enough that adding a 64-bit value of
+     log2 (1 + W_LO / (1 + W_HI)) will be a sufficient correction for
+     them.  */
+  long double w = x_frac - 1;
+  long double w_hi, w_lo;
+  int32_t se;
+  u_int32_t i0, i1;
+  GET_LDOUBLE_WORDS (se, i0, i1, w);
+  i0 &= 0xffff0000;
+  i1 = 0;
+  SET_LDOUBLE_WORDS (w_hi, se, i0, i1);
+  w_lo = w - w_hi;
+  long double wp = w_hi;
+  acc_split (&log_x_frac_hi, &log_x_frac_lo, log_x_frac_hi, log_x_frac_lo, wp);
+  wp *= -w_hi;
+  acc_split (&log_x_frac_hi, &log_x_frac_lo, log_x_frac_hi, log_x_frac_lo,
+	     wp / 2.0L);
+  wp *= -w_hi;
+  acc_split (&log_x_frac_hi, &log_x_frac_lo, log_x_frac_hi, log_x_frac_lo,
+	     wp * 0x0.5555p0L); /* -W_HI**3 / 3, high part.  */
+  acc_split (&log_x_frac_hi, &log_x_frac_lo, log_x_frac_hi, log_x_frac_lo,
+	     wp * 0x0.5555555555555555p-16L); /* -W_HI**3 / 3, low part.  */
+  wp *= -w_hi;
+  acc_split (&log_x_frac_hi, &log_x_frac_lo, log_x_frac_hi, log_x_frac_lo,
+	     wp / 4.0L);
+  /* Subsequent terms are small enough that they only need be computed
+     to 64 bits.  */
+  for (int i = 5; i <= 17; i++)
+    {
+      wp *= -w_hi;
+      acc_split (&log_x_frac_hi, &log_x_frac_lo, log_x_frac_hi, log_x_frac_lo,
+		 wp / i);
+    }
+
+  /* Convert LOG_X_FRAC_HI + LOG_X_FRAC_LO to a base-2 logarithm.  */
+  long double log2_x_frac_hi, log2_x_frac_lo;
+  long double log_x_frac_hi32, log_x_frac_lo64;
+  GET_LDOUBLE_WORDS (se, i0, i1, log_x_frac_hi);
+  i1 = 0;
+  SET_LDOUBLE_WORDS (log_x_frac_hi32, se, i0, i1);
+  log_x_frac_lo64 = (log_x_frac_hi - log_x_frac_hi32) + log_x_frac_lo;
+  long double log2_x_frac_hi1 = log_x_frac_hi32 * log2e_hi;
+  long double log2_x_frac_lo1
+    = log_x_frac_lo64 * log2e_hi + log_x_frac_hi * log2e_lo;
+  log2_x_frac_hi = log2_x_frac_hi1 + log2_x_frac_lo1;
+  log2_x_frac_lo = (log2_x_frac_hi1 - log2_x_frac_hi) + log2_x_frac_lo1;
+
+  /* Correct for the masking off of W_LO.  */
+  long double log2_1p_w_lo;
+  asm ("fyl2xp1"
+       : "=t" (log2_1p_w_lo)
+       : "0" (w_lo / (1.0L + w_hi)), "u" (1.0L)
+       : "st(1)");
+  acc_split (&log2_x_frac_hi, &log2_x_frac_lo, log2_x_frac_hi, log2_x_frac_lo,
+	     log2_1p_w_lo);
+
+  /* Correct for the masking off of X_FRAC_LOW.  */
+  acc_split (&log2_x_frac_hi, &log2_x_frac_lo, log2_x_frac_hi, log2_x_frac_lo,
+	     x_frac_low * M_LOG2El);
+
+  /* Add the integer and fractional parts of the base-2 logarithm.  */
+  long double log2_x_hi, log2_x_lo;
+  log2_x_hi = x_int_exponent + log2_x_frac_hi;
+  log2_x_lo = ((x_int_exponent - log2_x_hi) + log2_x_frac_hi) + log2_x_frac_lo;
+
+  /* Compute the base-2 logarithm of the result.  */
+  long double log2_res_hi, log2_res_lo;
+  long double log2_x_hi32, log2_x_lo64;
+  GET_LDOUBLE_WORDS (se, i0, i1, log2_x_hi);
+  i1 = 0;
+  SET_LDOUBLE_WORDS (log2_x_hi32, se, i0, i1);
+  log2_x_lo64 = (log2_x_hi - log2_x_hi32) + log2_x_lo;
+  long double y_hi32, y_lo32;
+  GET_LDOUBLE_WORDS (se, i0, i1, y);
+  i1 = 0;
+  SET_LDOUBLE_WORDS (y_hi32, se, i0, i1);
+  y_lo32 = y - y_hi32;
+  log2_res_hi = log2_x_hi32 * y_hi32;
+  log2_res_lo = log2_x_hi32 * y_lo32 + log2_x_lo64 * y;
+
+  /* Split the base-2 logarithm of the result into integer and
+     fractional parts.  */
+  long double log2_res_int = __roundl (log2_res_hi);
+  long double log2_res_frac = log2_res_hi - log2_res_int + log2_res_lo;
+  /* If the integer part is very large, the computed fractional part
+     may be outside the valid range for f2xm1.  */
+  if (fabsl (log2_res_int) > 16500)
+    log2_res_frac = 0;
+
+  /* Compute the final result.  */
+  long double res;
+  asm ("f2xm1" : "=t" (res) : "0" (log2_res_frac));
+  res += 1.0L;
+  if (negate)
+    res = -res;
+  asm ("fscale" : "=t" (res) : "0" (res), "u" (log2_res_int));
+  math_check_force_underflow (res);
+  return res;
+}
+
+libm_hidden_def (__powl_helper)
diff --git a/REORG.TODO/sysdeps/x86/fpu/test-fenv-clear-sse.c b/REORG.TODO/sysdeps/x86/fpu/test-fenv-clear-sse.c
new file mode 100644
index 0000000000..52a1b63c0b
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/test-fenv-clear-sse.c
@@ -0,0 +1,45 @@
+/* Test fesetenv (FE_DFL_ENV) and fesetenv (FE_NOMASK_ENV) clear
+   exceptions (bug 19181).  SSE version.
+   Copyright (C) 2015-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <cpuid.h>
+#include <stdbool.h>
+
+static bool
+have_sse2 (void)
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return false;
+
+  return (edx & bit_SSE2) != 0;
+}
+
+#define CHECK_CAN_TEST						\
+  do								\
+    {								\
+      if (!have_sse2 ())					\
+	{							\
+	  puts ("CPU does not support SSE2, cannot test");	\
+	  return 0;						\
+	}							\
+    }								\
+  while (0)
+
+#include <test-fenv-clear-main.c>
diff --git a/REORG.TODO/sysdeps/x86/fpu/test-fenv-sse-2.c b/REORG.TODO/sysdeps/x86/fpu/test-fenv-sse-2.c
new file mode 100644
index 0000000000..b5f96850f9
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/test-fenv-sse-2.c
@@ -0,0 +1,176 @@
+/* Test x86-specific floating-point environment (bug 16068): SSE part.
+   Copyright (C) 2015-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <cpuid.h>
+#include <fenv.h>
+#include <float.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+
+static bool
+have_sse2 (void)
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return false;
+
+  return (edx & bit_SSE2) != 0;
+}
+
+static uint32_t
+get_sse_mxcsr (void)
+{
+  uint32_t temp;
+  __asm__ __volatile__ ("stmxcsr %0" : "=m" (temp));
+  return temp;
+}
+
+static void
+set_sse_mxcsr (uint32_t val)
+{
+  __asm__ __volatile__ ("ldmxcsr %0" : : "m" (val));
+}
+
+static void
+set_sse_mxcsr_bits (uint32_t mask, uint32_t bits)
+{
+  uint32_t mxcsr = get_sse_mxcsr ();
+  mxcsr = (mxcsr & ~mask) | bits;
+  set_sse_mxcsr (mxcsr);
+}
+
+static int
+test_sse_mxcsr_bits (const char *test, uint32_t mask, uint32_t bits)
+{
+  uint32_t mxcsr = get_sse_mxcsr ();
+  printf ("Testing %s: mxcsr = %x\n", test, mxcsr);
+  if ((mxcsr & mask) == bits)
+    {
+      printf ("PASS: %s\n", test);
+      return 0;
+    }
+  else
+    {
+      printf ("FAIL: %s\n", test);
+      return 1;
+    }
+}
+
+#define MXCSR_FZ 0x8000
+#define MXCSR_DAZ 0x40
+#define MXCSR_DE 0x2
+#define MXCSR_DM 0x100
+
+static __attribute__ ((noinline)) int
+sse_tests (void)
+{
+  int result = 0;
+  fenv_t env1, env2;
+  /* Test FZ bit.  */
+  fegetenv (&env1);
+  set_sse_mxcsr_bits (MXCSR_FZ, MXCSR_FZ);
+  fegetenv (&env2);
+  fesetenv (&env1);
+  result |= test_sse_mxcsr_bits ("fesetenv FZ restoration",
+				 MXCSR_FZ, 0);
+  set_sse_mxcsr_bits (MXCSR_FZ, 0);
+  fesetenv (&env2);
+  result |= test_sse_mxcsr_bits ("fesetenv FZ restoration 2",
+				 MXCSR_FZ, MXCSR_FZ);
+  set_sse_mxcsr_bits (MXCSR_FZ, MXCSR_FZ);
+  fesetenv (FE_NOMASK_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_NOMASK_ENV) FZ restoration",
+				 MXCSR_FZ, 0);
+  set_sse_mxcsr_bits (MXCSR_FZ, MXCSR_FZ);
+  fesetenv (FE_DFL_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_DFL_ENV) FZ restoration",
+				 MXCSR_FZ, 0);
+  /* Test DAZ bit.  */
+  set_sse_mxcsr_bits (MXCSR_DAZ, MXCSR_DAZ);
+  fegetenv (&env2);
+  fesetenv (&env1);
+  result |= test_sse_mxcsr_bits ("fesetenv DAZ restoration",
+				 MXCSR_DAZ, 0);
+  set_sse_mxcsr_bits (MXCSR_DAZ, 0);
+  fesetenv (&env2);
+  result |= test_sse_mxcsr_bits ("fesetenv DAZ restoration 2",
+				 MXCSR_DAZ, MXCSR_DAZ);
+  set_sse_mxcsr_bits (MXCSR_DAZ, MXCSR_DAZ);
+  fesetenv (FE_NOMASK_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_NOMASK_ENV) DAZ restoration",
+				 MXCSR_DAZ, 0);
+  set_sse_mxcsr_bits (MXCSR_DAZ, MXCSR_DAZ);
+  fesetenv (FE_DFL_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_DFL_ENV) DAZ restoration",
+				 MXCSR_DAZ, 0);
+  /* Test DM bit.  */
+  set_sse_mxcsr_bits (MXCSR_DM, 0);
+  fegetenv (&env2);
+  fesetenv (&env1);
+  result |= test_sse_mxcsr_bits ("fesetenv DM restoration",
+				 MXCSR_DM, MXCSR_DM);
+  set_sse_mxcsr_bits (MXCSR_DM, MXCSR_DM);
+  fesetenv (&env2);
+  result |= test_sse_mxcsr_bits ("fesetenv DM restoration 2",
+				 MXCSR_DM, 0);
+  set_sse_mxcsr_bits (MXCSR_DM, 0);
+  /* Presume FE_NOMASK_ENV should leave the "denormal operand"
+     exception masked, as not a standard exception.  */
+  fesetenv (FE_NOMASK_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_NOMASK_ENV) DM restoration",
+				 MXCSR_DM, MXCSR_DM);
+  set_sse_mxcsr_bits (MXCSR_DM, 0);
+  fesetenv (FE_DFL_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_DFL_ENV) DM restoration",
+				 MXCSR_DM, MXCSR_DM);
+  /* Test DE bit.  */
+  set_sse_mxcsr_bits (MXCSR_DE, MXCSR_DE);
+  fegetenv (&env2);
+  fesetenv (&env1);
+  result |= test_sse_mxcsr_bits ("fesetenv DE restoration",
+				 MXCSR_DE, 0);
+  set_sse_mxcsr_bits (MXCSR_DE, 0);
+  fesetenv (&env2);
+  result |= test_sse_mxcsr_bits ("fesetenv DE restoration 2",
+				 MXCSR_DE, MXCSR_DE);
+  set_sse_mxcsr_bits (MXCSR_DE, MXCSR_DE);
+  fesetenv (FE_NOMASK_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_NOMASK_ENV) DE restoration",
+				 MXCSR_DE, 0);
+  set_sse_mxcsr_bits (MXCSR_DE, MXCSR_DE);
+  fesetenv (FE_DFL_ENV);
+  result |= test_sse_mxcsr_bits ("fesetenv (FE_DFL_ENV) DE restoration",
+				 MXCSR_DE, 0);
+  return result;
+}
+
+static int
+do_test (void)
+{
+  if (!have_sse2 ())
+    {
+      puts ("CPU does not support SSE2, cannot test");
+      return 0;
+    }
+  return sse_tests ();
+}
+
+#define TEST_FUNCTION do_test ()
+#include <test-skeleton.c>
diff --git a/REORG.TODO/sysdeps/x86/fpu/test-fenv-sse.c b/REORG.TODO/sysdeps/x86/fpu/test-fenv-sse.c
new file mode 100644
index 0000000000..569db9a674
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/test-fenv-sse.c
@@ -0,0 +1,138 @@
+/* Test floating-point environment includes SSE state (bug 16064).
+   Copyright (C) 2014-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <cpuid.h>
+#include <fenv.h>
+#include <float.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+static bool
+have_sse2 (void)
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return false;
+
+  return (edx & bit_SSE2) != 0;
+}
+
+static __attribute__ ((noinline)) int
+sse_tests (void)
+{
+  int ret = 0;
+  fenv_t base_env;
+  if (fegetenv (&base_env) != 0)
+    {
+      puts ("fegetenv (&base_env) failed");
+      return 1;
+    }
+  if (fesetround (FE_UPWARD) != 0)
+    {
+      puts ("fesetround (FE_UPWARD) failed");
+      return 1;
+    }
+  if (fesetenv (&base_env) != 0)
+    {
+      puts ("fesetenv (&base_env) failed");
+      return 1;
+    }
+  volatile float a = 1.0f, b = FLT_MIN, c;
+  c = a + b;
+  if (c != 1.0f)
+    {
+      puts ("fesetenv did not restore rounding mode");
+      ret = 1;
+    }
+  if (fesetround (FE_DOWNWARD) != 0)
+    {
+      puts ("fesetround (FE_DOWNWARD) failed");
+      return 1;
+    }
+  if (feupdateenv (&base_env) != 0)
+    {
+      puts ("feupdateenv (&base_env) failed");
+      return 1;
+    }
+  volatile float d = -FLT_MIN, e;
+  e = a + d;
+  if (e != 1.0f)
+    {
+      puts ("feupdateenv did not restore rounding mode");
+      ret = 1;
+    }
+  if (fesetround (FE_UPWARD) != 0)
+    {
+      puts ("fesetround (FE_UPWARD) failed");
+      return 1;
+    }
+  fenv_t upward_env;
+  if (feholdexcept (&upward_env) != 0)
+    {
+      puts ("feholdexcept (&upward_env) failed");
+      return 1;
+    }
+  if (fesetround (FE_DOWNWARD) != 0)
+    {
+      puts ("fesetround (FE_DOWNWARD) failed");
+      return 1;
+    }
+  if (fesetenv (&upward_env) != 0)
+    {
+      puts ("fesetenv (&upward_env) failed");
+      return 1;
+    }
+  e = a + d;
+  if (e != 1.0f)
+    {
+      puts ("fesetenv did not restore rounding mode from feholdexcept");
+      ret = 1;
+    }
+  if (fesetround (FE_UPWARD) != 0)
+    {
+      puts ("fesetround (FE_UPWARD) failed");
+      return 1;
+    }
+  if (fesetenv (FE_DFL_ENV) != 0)
+    {
+      puts ("fesetenv (FE_DFL_ENV) failed");
+      return 1;
+    }
+  c = a + b;
+  if (c != 1.0f)
+    {
+      puts ("fesetenv (FE_DFL_ENV) did not restore rounding mode");
+      ret = 1;
+    }
+  return ret;
+}
+
+static int
+do_test (void)
+{
+  if (!have_sse2 ())
+    {
+      puts ("CPU does not support SSE2, cannot test");
+      return 0;
+    }
+  return sse_tests ();
+}
+
+#define TEST_FUNCTION do_test ()
+#include <test-skeleton.c>
diff --git a/REORG.TODO/sysdeps/x86/fpu/test-fenv-x87.c b/REORG.TODO/sysdeps/x86/fpu/test-fenv-x87.c
new file mode 100644
index 0000000000..29ae1c8a7e
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/test-fenv-x87.c
@@ -0,0 +1,169 @@
+/* Test x86-specific floating-point environment (bug 16068): x87 part.
+   Copyright (C) 2015-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <fenv.h>
+#include <float.h>
+#include <fpu_control.h>
+#include <stdint.h>
+#include <stdio.h>
+
+static uint16_t
+get_x87_cw (void)
+{
+  fpu_control_t cw;
+  _FPU_GETCW (cw);
+  return cw;
+}
+
+static void
+set_x87_cw (uint16_t val)
+{
+  fpu_control_t cw = val;
+  _FPU_SETCW (cw);
+}
+
+static void
+set_x87_cw_bits (uint16_t mask, uint16_t bits)
+{
+  uint16_t cw = get_x87_cw ();
+  cw = (cw & ~mask) | bits;
+  set_x87_cw (cw);
+}
+
+static int
+test_x87_cw_bits (const char *test, uint16_t mask, uint16_t bits)
+{
+  uint16_t cw = get_x87_cw ();
+  printf ("Testing %s: cw = %x\n", test, cw);
+  if ((cw & mask) == bits)
+    {
+      printf ("PASS: %s\n", test);
+      return 0;
+    }
+  else
+    {
+      printf ("FAIL: %s\n", test);
+      return 1;
+    }
+}
+
+static uint16_t
+get_x87_sw (void)
+{
+  uint16_t temp;
+  __asm__ __volatile__ ("fnstsw %0" : "=a" (temp));
+  return temp;
+}
+
+static void
+set_x87_sw_bits (uint16_t mask, uint16_t bits)
+{
+  fenv_t temp;
+  __asm__ __volatile__ ("fnstenv %0" : "=m" (temp));
+  temp.__status_word = (temp.__status_word & ~mask) | bits;
+  __asm__ __volatile__ ("fldenv %0" : : "m" (temp));
+}
+
+static int
+test_x87_sw_bits (const char *test, uint16_t mask, uint16_t bits)
+{
+  uint16_t sw = get_x87_sw ();
+  printf ("Testing %s: sw = %x\n", test, sw);
+  if ((sw & mask) == bits)
+    {
+      printf ("PASS: %s\n", test);
+      return 0;
+    }
+  else
+    {
+      printf ("FAIL: %s\n", test);
+      return 1;
+    }
+}
+
+#define X87_CW_PREC_MASK _FPU_EXTENDED
+
+static int
+do_test (void)
+{
+  int result = 0;
+  fenv_t env1, env2;
+  /* Test precision mask.  */
+  fegetenv (&env1);
+  set_x87_cw_bits (X87_CW_PREC_MASK, _FPU_SINGLE);
+  fegetenv (&env2);
+  fesetenv (&env1);
+  result |= test_x87_cw_bits ("fesetenv precision restoration",
+			      X87_CW_PREC_MASK, _FPU_EXTENDED);
+  set_x87_cw_bits (X87_CW_PREC_MASK, _FPU_EXTENDED);
+  fesetenv (&env2);
+  result |= test_x87_cw_bits ("fesetenv precision restoration 2",
+			      X87_CW_PREC_MASK, _FPU_SINGLE);
+  set_x87_cw_bits (X87_CW_PREC_MASK, _FPU_DOUBLE);
+  fesetenv (FE_NOMASK_ENV);
+  result |= test_x87_cw_bits ("fesetenv (FE_NOMASK_ENV) precision restoration",
+			      X87_CW_PREC_MASK, _FPU_EXTENDED);
+  set_x87_cw_bits (X87_CW_PREC_MASK, _FPU_SINGLE);
+  fesetenv (FE_DFL_ENV);
+  result |= test_x87_cw_bits ("fesetenv (FE_DFL_ENV) precision restoration",
+			      X87_CW_PREC_MASK, _FPU_EXTENDED);
+  /* Test x87 denormal operand masking.  */
+  set_x87_cw_bits (_FPU_MASK_DM, 0);
+  fegetenv (&env2);
+  fesetenv (&env1);
+  result |= test_x87_cw_bits ("fesetenv denormal mask restoration",
+			      _FPU_MASK_DM, _FPU_MASK_DM);
+  set_x87_cw_bits (_FPU_MASK_DM, _FPU_MASK_DM);
+  fesetenv (&env2);
+  result |= test_x87_cw_bits ("fesetenv denormal mask restoration 2",
+			      _FPU_MASK_DM, 0);
+  set_x87_cw_bits (_FPU_MASK_DM, 0);
+  /* Presume FE_NOMASK_ENV should leave the "denormal operand"
+     exception masked, as not a standard exception.  */
+  fesetenv (FE_NOMASK_ENV);
+  result |= test_x87_cw_bits ("fesetenv (FE_NOMASK_ENV) denormal mask "
+			      "restoration",
+			      _FPU_MASK_DM, _FPU_MASK_DM);
+  set_x87_cw_bits (_FPU_MASK_DM, 0);
+  fesetenv (FE_DFL_ENV);
+  result |= test_x87_cw_bits ("fesetenv (FE_DFL_ENV) denormal mask "
+			      "restoration",
+			      _FPU_MASK_DM, _FPU_MASK_DM);
+  /* Test x87 denormal operand exception.  */
+  set_x87_sw_bits (__FE_DENORM, __FE_DENORM);
+  fegetenv (&env2);
+  fesetenv (&env1);
+  result |= test_x87_sw_bits ("fesetenv denormal exception restoration",
+			      __FE_DENORM, 0);
+  set_x87_sw_bits (__FE_DENORM, 0);
+  fesetenv (&env2);
+  result |= test_x87_sw_bits ("fesetenv denormal exception restoration 2",
+			      __FE_DENORM, __FE_DENORM);
+  set_x87_sw_bits (__FE_DENORM, __FE_DENORM);
+  fesetenv (FE_NOMASK_ENV);
+  result |= test_x87_sw_bits ("fesetenv (FE_NOMASK_ENV) exception restoration",
+			      __FE_DENORM, 0);
+  set_x87_sw_bits (__FE_DENORM, __FE_DENORM);
+  fesetenv (FE_DFL_ENV);
+  result |= test_x87_sw_bits ("fesetenv (FE_DFL_ENV) exception restoration",
+			      __FE_DENORM, 0);
+  return result;
+}
+
+#define TEST_FUNCTION do_test ()
+#include <test-skeleton.c>
diff --git a/REORG.TODO/sysdeps/x86/fpu/test-flt-eval-method-387.c b/REORG.TODO/sysdeps/x86/fpu/test-flt-eval-method-387.c
new file mode 100644
index 0000000000..2fb7acfb76
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/test-flt-eval-method-387.c
@@ -0,0 +1 @@
+#include <test-flt-eval-method.c>
diff --git a/REORG.TODO/sysdeps/x86/fpu/test-flt-eval-method-sse.c b/REORG.TODO/sysdeps/x86/fpu/test-flt-eval-method-sse.c
new file mode 100644
index 0000000000..2fb7acfb76
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/test-flt-eval-method-sse.c
@@ -0,0 +1 @@
+#include <test-flt-eval-method.c>
diff --git a/REORG.TODO/sysdeps/x86/fpu/test-math-vector-sincos.h b/REORG.TODO/sysdeps/x86/fpu/test-math-vector-sincos.h
new file mode 100644
index 0000000000..95282a3ac7
--- /dev/null
+++ b/REORG.TODO/sysdeps/x86/fpu/test-math-vector-sincos.h
@@ -0,0 +1,98 @@
+/* Wrappers definitions for tests of ABI of vector sincos/sincosf having
+   vector declaration "#pragma omp declare simd notinbranch".
+   Copyright (C) 2016-2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#define INIT_VEC_PTRS_LOOP(vec, val, len)				\
+  do									\
+    {									\
+      union { VEC_INT_TYPE v; __typeof__ ((val)[0]) *a[(len)]; } u;	\
+      for (i = 0; i < len; i++)						\
+	u.a[i] = &(val)[i];						\
+      (vec) = u.v;							\
+    }									\
+  while (0)
+
+/* Wrapper for vector sincos/sincosf compatible with x86_64 and x32 variants
+   of _ZGVbN2vvv_sincos, _ZGVdN4vvv_sincos, _ZGVeN8vvv_sincos;
+   x32 variants of _ZGVbN4vvv_sincosf, _ZGVcN4vvv_sincos, _ZGVdN8vvv_sincosf,
+   _ZGVeN16vvv_sincosf.  */
+#define VECTOR_WRAPPER_fFF_2(scalar_func, vector_func)		\
+extern void vector_func (VEC_TYPE, VEC_INT_TYPE, VEC_INT_TYPE);	\
+void scalar_func (FLOAT x, FLOAT * r, FLOAT * r1)		\
+{								\
+  int i;							\
+  FLOAT r_loc[VEC_LEN], r1_loc[VEC_LEN];			\
+  VEC_TYPE mx;							\
+  VEC_INT_TYPE mr, mr1;						\
+  INIT_VEC_LOOP (mx, x, VEC_LEN);				\
+  INIT_VEC_PTRS_LOOP (mr, r_loc, VEC_LEN);			\
+  INIT_VEC_PTRS_LOOP (mr1, r1_loc, VEC_LEN);			\
+  vector_func (mx, mr, mr1);					\
+  TEST_VEC_LOOP (r_loc, VEC_LEN);				\
+  TEST_VEC_LOOP (r1_loc, VEC_LEN);				\
+  *r = r_loc[0];						\
+  *r1 = r1_loc[0];						\
+  return;							\
+}
+
+/* Wrapper for vector sincos/sincosf compatible with x86_64 variants of
+   _ZGVcN4vvv_sincos, _ZGVeN16vvv_sincosf, _ZGVbN4vvv_sincosf,
+   _ZGVdN8vvv_sincosf, _ZGVcN8vvv_sincosf.  */
+#define VECTOR_WRAPPER_fFF_3(scalar_func, vector_func)		\
+extern void vector_func (VEC_TYPE, VEC_INT_TYPE, VEC_INT_TYPE,  \
+			 VEC_INT_TYPE, VEC_INT_TYPE);		\
+void scalar_func (FLOAT x, FLOAT * r, FLOAT * r1)		\
+{								\
+  int i;							\
+  FLOAT r_loc[VEC_LEN/2], r1_loc[VEC_LEN/2];			\
+  VEC_TYPE mx;							\
+  VEC_INT_TYPE mr, mr1;						\
+  INIT_VEC_LOOP (mx, x, VEC_LEN);				\
+  INIT_VEC_PTRS_LOOP (mr, r_loc, VEC_LEN/2);			\
+  INIT_VEC_PTRS_LOOP (mr1, r1_loc, VEC_LEN/2);			\
+  vector_func (mx, mr, mr, mr1, mr1);				\
+  TEST_VEC_LOOP (r_loc, VEC_LEN/2);				\
+  TEST_VEC_LOOP (r1_loc, VEC_LEN/2);				\
+  *r = r_loc[0];						\
+  *r1 = r1_loc[0];						\
+  return;							\
+}
+
+/* Wrapper for vector sincosf compatible with x86_64 variant of
+   _ZGVcN8vvv_sincosf.  */
+#define VECTOR_WRAPPER_fFF_4(scalar_func, vector_func) 		\
+extern void vector_func (VEC_TYPE, VEC_INT_TYPE, VEC_INT_TYPE,	\
+			 VEC_INT_TYPE, VEC_INT_TYPE,		\
+			 VEC_INT_TYPE, VEC_INT_TYPE,		\
+			 VEC_INT_TYPE, VEC_INT_TYPE);		\
+void scalar_func (FLOAT x, FLOAT * r, FLOAT * r1)		\
+{								\
+  int i;							\
+  FLOAT r_loc[VEC_LEN/4], r1_loc[VEC_LEN/4];			\
+  VEC_TYPE mx;							\
+  VEC_INT_TYPE mr, mr1;						\
+  INIT_VEC_LOOP (mx, x, VEC_LEN);				\
+  INIT_VEC_PTRS_LOOP (mr, r_loc, VEC_LEN/4);			\
+  INIT_VEC_PTRS_LOOP (mr1, r1_loc, VEC_LEN/4);			\
+  vector_func (mx, mr, mr, mr, mr, mr1, mr1, mr1, mr1);		\
+  TEST_VEC_LOOP (r_loc, VEC_LEN/4);				\
+  TEST_VEC_LOOP (r1_loc, VEC_LEN/4);				\
+  *r = r_loc[0];						\
+  *r1 = r1_loc[0];						\
+  return;							\
+}