opcodes:

	* cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to
	CGEN_INSN_RELAXED.
	* fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate.
	* frv-asm.c,frv-desc.c,frv-desc.h: Regenerate.
	* ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate.
	* iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate.
	* m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate.
	* openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate.
	* xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate.
gas:
	* cgen.c (gas_cgen_finish_insn): CGEN_INSN_RELAX renamed to
	CGEN_INSN_RELAXED.
	* config/tc-fr30.c (md_estimate_size_before_relax): Ditto.
	* config/tc-m32r.c (md_estimate_size_before_relax): Ditto.
	* config/tc-openrisc.c (md_estimate_size_before_relax): Ditto.

24 files changed, 48 insertions, 36 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4ca1d76f70a..22e270394e0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2003-06-10  Doug Evans  <dje@sebabeach.org>
+
+	* cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to
+	CGEN_INSN_RELAXED.
+	* fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate.
+	* frv-asm.c,frv-desc.c,frv-desc.h: Regenerate.
+	* ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate.
+	* iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate.
+	* m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate.
+	* openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate.
+	* xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate.
+
 2003-06-10  Gary Hade <garyhade@us.ibm.com>
 	    Alan Modra  <amodra@bigpond.net.au>
 
diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in
index 525177c79d0..1ea076809b9 100644
--- a/opcodes/cgen-asm.in
+++ b/opcodes/cgen-asm.in
@@ -361,10 +361,10 @@ const CGEN_INSN *
       if (! @arch@_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index be9c36c947c..8e7c7b80975 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -657,10 +657,10 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! fr30_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c
index 01d896f28ea..3309d54cf03 100644
--- a/opcodes/fr30-desc.c
+++ b/opcodes/fr30-desc.c
@@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h
index 6be96d933ab..35d0de70820 100644
--- a/opcodes/fr30-desc.h
+++ b/opcodes/fr30-desc.h
@@ -240,7 +240,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c
index b4647b1ed4d..0e3d8ddf669 100644
--- a/opcodes/frv-asm.c
+++ b/opcodes/frv-asm.c
@@ -960,10 +960,10 @@ frv_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! frv_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c
index ffb0b27e3b9..97d49b3077b 100644
--- a/opcodes/frv-desc.c
+++ b/opcodes/frv-desc.c
@@ -188,7 +188,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h
index 3ecf0913aa1..a169e7a6092 100644
--- a/opcodes/frv-desc.h
+++ b/opcodes/frv-desc.h
@@ -696,7 +696,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING
  , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS
  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR
diff --git a/opcodes/ip2k-asm.c b/opcodes/ip2k-asm.c
index 6a1653b014b..524f256a537 100644
--- a/opcodes/ip2k-asm.c
+++ b/opcodes/ip2k-asm.c
@@ -908,10 +908,10 @@ ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! ip2k_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/ip2k-desc.c b/opcodes/ip2k-desc.c
index f8e493289fb..0ab2cc5fa44 100644
--- a/opcodes/ip2k-desc.c
+++ b/opcodes/ip2k-desc.c
@@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "EXT-SKIP-INSN", &bool_attr[0], &bool_attr[0] },
diff --git a/opcodes/ip2k-desc.h b/opcodes/ip2k-desc.h
index 84db7fb1cb0..11220263b5c 100644
--- a/opcodes/ip2k-desc.h
+++ b/opcodes/ip2k-desc.h
@@ -225,7 +225,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA
  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c
index bb61af0c3d0..7fb795eb155 100644
--- a/opcodes/iq2000-asm.c
+++ b/opcodes/iq2000-asm.c
@@ -794,10 +794,10 @@ iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! iq2000_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/iq2000-desc.c b/opcodes/iq2000-desc.c
index 402f7268d1f..6c7f3b06b79 100644
--- a/opcodes/iq2000-desc.c
+++ b/opcodes/iq2000-desc.c
@@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "YIELD-INSN", &bool_attr[0], &bool_attr[0] },
diff --git a/opcodes/iq2000-desc.h b/opcodes/iq2000-desc.h
index fe3a5e3f6ab..13b4f56a80b 100644
--- a/opcodes/iq2000-desc.h
+++ b/opcodes/iq2000-desc.h
@@ -273,7 +273,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY
  , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS
  , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 4abe187b81f..2bd751af6db 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -659,10 +659,10 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! m32r_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 30a071985bd..023ab62bb9e 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -118,7 +118,7 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h
index 85e22ee4dcd..8781772f266 100644
--- a/opcodes/m32r-desc.h
+++ b/opcodes/m32r-desc.h
@@ -204,7 +204,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE
  , CGEN_INSN_END_NBOOLS
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index b60c1bf36e0..8143b618520 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -1187,7 +1187,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bc $disp24 */
   {
     -1, "bc24r", "bc", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bl $disp8 */
   {
@@ -1197,7 +1197,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bl $disp24 */
   {
     -1, "bl24r", "bl", 32,
-    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bcl $disp8 */
   {
@@ -1207,7 +1207,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bcl $disp24 */
   {
     -1, "bcl24r", "bcl", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* bnc $disp8 */
   {
@@ -1217,7 +1217,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bnc $disp24 */
   {
     -1, "bnc24r", "bnc", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bra $disp8 */
   {
@@ -1227,7 +1227,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bra $disp24 */
   {
     -1, "bra24r", "bra", 32,
-    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bncl $disp8 */
   {
@@ -1237,7 +1237,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bncl $disp24 */
   {
     -1, "bncl24r", "bncl", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* ld $dr,@($sr) */
   {
diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c
index d47659b8c8f..26b2625957f 100644
--- a/opcodes/openrisc-asm.c
+++ b/opcodes/openrisc-asm.c
@@ -578,10 +578,10 @@ openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! openrisc_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
index 6de9107f77b..989b1958648 100644
--- a/opcodes/openrisc-desc.c
+++ b/opcodes/openrisc-desc.c
@@ -112,7 +112,7 @@ const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h
index d1edee2f51c..0c7df17b886 100644
--- a/opcodes/openrisc-desc.h
+++ b/opcodes/openrisc-desc.h
@@ -223,7 +223,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c
index 324c091893e..810938c4a93 100644
--- a/opcodes/xstormy16-asm.c
+++ b/opcodes/xstormy16-asm.c
@@ -618,10 +618,10 @@ xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! xstormy16_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c
index 9c9f30bc582..1c94fd7d853 100644
--- a/opcodes/xstormy16-desc.c
+++ b/opcodes/xstormy16-desc.c
@@ -104,7 +104,7 @@ const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { 0, 0, 0 }
diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h
index a880321f759..e6135058083 100644
--- a/opcodes/xstormy16-desc.h
+++ b/opcodes/xstormy16-desc.h
@@ -261,7 +261,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;