gas/

	* config/tc-mips.c (is_opcode_valid): Remove expansionp.
	(macro_build): Change invocation of is_opcode_valid.
	(mips_ip): Likewise.

	gas/testsuite/
	* gas/mips/mips-no-jalx.l: Delete.
	* gas/mips/mips-no-jalx.s: Delete.
	* gas/mips/mips-jalx-2.d: New.
	* gas/mips/mips-jalx-2.s: New.
	* gas/mips/mips.exp (mips-jalx-2): Run new test.
	(mips-no-jalx): Remove deleted test.

	include/
	* opcode/mips.h (INSN_MIPS16): Remove.

	opcodes/
	* mips-dis.c (mips_arch): Remove INSN_MIPS16.
	* mips-opc.c (I16): Remove.
	(mips_builtin_op): Reclassify jalx.

5 files changed, 19 insertions, 11 deletions

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 915e2f72351..431598b2a78 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2010-05-26  Catherine Moore  <clm@codesourcery.com>
+
+	* opcode/mips.h (INSN_MIPS16): Remove.
+
 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 
 	* tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index c2f16d65b84..45085bda71c 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -555,8 +555,9 @@ static const unsigned int mips_isa_table[] =
 /* DSP ASE */ 
 #define INSN_DSP                  0x00001000
 #define INSN_DSP64                0x00002000
-/* MIPS 16 ASE */
-#define INSN_MIPS16               0x00004000
+
+/* 0x00004000 is unused.  */
+
 /* MIPS-3D ASE */
 #define INSN_MIPS3D               0x00008000
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6725e021bc0..29dd2950650 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2010-05-26  Catherine Moore  <clm@codesoourcery.com>
+
+	* mips-dis.c (mips_arch): Remove INSN_MIPS16.
+	* mips-opc.c (I16): Remove.
+	(mips_builtin_op): Reclassify jalx.
+
 2010-05-19  Alan Modra  <amodra@gmail.com>
 
 	* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 203f29fb775..bcfef7237eb 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -472,13 +472,13 @@ const struct mips_arch_choice mips_arch_choices[] =
      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
      page 1.  */
   { "mips32",	1, bfd_mach_mipsisa32, CPU_MIPS32,
-    ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
+    ISA_MIPS32 | INSN_SMARTMIPS,
     mips_cp0_names_mips3264,
     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
     mips_hwr_names_numeric },
 
   { "mips32r2",	1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
-    (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
+    (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
      | INSN_MIPS3D | INSN_MT),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
@@ -486,13 +486,13 @@ const struct mips_arch_choice mips_arch_choices[] =
 
   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
   { "mips64",	1, bfd_mach_mipsisa64, CPU_MIPS64,
-    ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
+    ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
     mips_cp0_names_mips3264,
     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
     mips_hwr_names_numeric },
 
   { "mips64r2",	1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
-    (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
+    (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
      | INSN_DSP64 | INSN_MT | INSN_MDMX),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
@@ -524,7 +524,7 @@ const struct mips_arch_choice mips_arch_choices[] =
 
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
-  { "",		1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
+  { "",		1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
 };
 
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 6278a205661..fafcb12d376 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -96,9 +96,6 @@
 #define I4_33   INSN_ISA4_32R2
 #define I5_33   INSN_ISA5_32R2
 
-/* MIPS16 ASE support.  */
-#define I16     INSN_MIPS16
-
 /* MIPS64 MIPS-3D ASE support.  */
 #define M3D     INSN_MIPS3D
 
@@ -739,7 +736,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31,		0,		I1	},
-{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		0,		I16     },
+{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		0,		I1	},
 {"la",      "t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		0,		I1	},
 {"lb",      "t,o(b)",	0x80000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
 {"lb",      "t,A(b)",	0,    (int) M_LB_AB,	INSN_MACRO,		0,		I1	},