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/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O -march=armv8-a+sve" } */
#include "sve_uzp1_1.c"
#define TEST_UZP1(TYPE, EXPECTED_RESULT, VALUES1, VALUES2) \
{ \
TYPE expected_result = EXPECTED_RESULT; \
TYPE values1 = VALUES1; \
TYPE values2 = VALUES2; \
TYPE dest; \
dest = uzp1_##TYPE (values1, values2); \
if (__builtin_memcmp (&dest, &expected_result, sizeof (TYPE)) != 0) \
__builtin_abort (); \
}
int main (void)
{
TEST_UZP1 (v4di,
((v4di) { 4, 6, 12, 36 }),
((v4di) { 4, 5, 6, 7 }),
((v4di) { 12, 24, 36, 48 }));
TEST_UZP1 (v8si,
((v8si) { 3, 5, 7, 9, 33, 35, 37, 39 }),
((v8si) { 3, 4, 5, 6, 7, 8, 9, 10 }),
((v8si) { 33, 34, 35, 36, 37, 38, 39, 40 }));
TEST_UZP1 (v16hi,
((v16hi) { 3, 5, 7, 9, 11, 13, 15, 17,
33, 35, 37, 39, 41, 43, 45, 47 }),
((v16hi) { 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15, 16, 17, 18 }),
((v16hi) { 33, 34, 35, 36, 37, 38, 39, 40,
41, 42, 43, 44, 45, 46, 47, 48 }));
TEST_UZP1 (v32qi,
((v32qi) { 4, 6, 4, 6, 4, 6, 4, 6,
4, 6, 4, 6, 4, 6, 4, 6,
12, 36, 12, 36, 12, 36, 12, 36,
12, 36, 12, 36, 12, 36, 12, 36 }),
((v32qi) { 4, 5, 6, 7, 4, 5, 6, 7,
4, 5, 6, 7, 4, 5, 6, 7,
4, 5, 6, 7, 4, 5, 6, 7,
4, 5, 6, 7, 4, 5, 6, 7 }),
((v32qi) { 12, 24, 36, 48, 12, 24, 36, 48,
12, 24, 36, 48, 12, 24, 36, 48,
12, 24, 36, 48, 12, 24, 36, 48,
12, 24, 36, 48, 12, 24, 36, 48 }));
TEST_UZP1 (v4df,
((v4df) { 4.0, 6.0, 12.0, 36.0 }),
((v4df) { 4.0, 5.0, 6.0, 7.0 }),
((v4df) { 12.0, 24.0, 36.0, 48.0 }));
TEST_UZP1 (v8sf,
((v8sf) { 3.0, 5.0, 7.0, 9.0, 33.0, 35.0, 37.0, 39.0 }),
((v8sf) { 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 }),
((v8sf) { 33.0, 34.0, 35.0, 36.0, 37.0, 38.0, 39.0, 40.0 }));
TEST_UZP1 (v16hf,
((v16hf) { 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0, 17.0,
33.0, 35.0, 37.0, 39.0, 41.0, 43.0, 45.0, 47.0 }),
((v16hf) { 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0,
11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0 }),
((v16hf) { 33.0, 34.0, 35.0, 36.0, 37.0, 38.0, 39.0, 40.0,
41.0, 42.0, 43.0, 44.0, 45.0, 46.0, 47.0, 48.0 }));
return 0;
}
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