summaryrefslogtreecommitdiff
path: root/gcc/testsuite/gcc.target/aarch64/sve_slp_11_run.c
blob: c302ef6fb766993b6d1cb826756e28700d74aadb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve" } */

#include "sve_slp_11.c"

#define N1 (103 * 2)
#define N2 (111 * 2)

#define HARNESS(TYPE1, TYPE2)					\
  {								\
    TYPE1 a[N2];						\
    TYPE2 b[N2 * 2];						\
    for (unsigned int i = 0; i < N2; ++i)			\
      {								\
	a[i] = i * 2 + i % 5;					\
	b[i * 2] = i * 3 + i % 7;				\
	b[i * 2 + 1] = i * 5 + i % 9;				\
      }								\
    vec_slp_##TYPE1##_##TYPE2 (a, b, N1 / 2);			\
    for (unsigned int i = 0; i < N2; ++i)			\
      {								\
	TYPE1 orig_a = i * 2 + i % 5;				\
	TYPE2 orig_b1 = i * 3 + i % 7;				\
	TYPE2 orig_b2 = i * 5 + i % 9;				\
	TYPE1 expected_a = orig_a;				\
	TYPE2 expected_b1 = orig_b1;				\
	TYPE2 expected_b2 = orig_b2;				\
	if (i < N1)						\
	  {							\
	    expected_a += i & 1 ? 2 : 1;			\
	    expected_b1 += i & 1 ? 5 : 3;			\
	    expected_b2 += i & 1 ? 6 : 4;			\
	  }							\
	if (a[i] != expected_a					\
	    || b[i * 2] != expected_b1				\
	    || b[i * 2 + 1] != expected_b2)			\
	  __builtin_abort ();					\
      }								\
  }

int
main (void)
{
  TEST_ALL (HARNESS)
}