blob: 44dff49e3867200a63c7c8dddc7a27130619ac2f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
;; Scheduling description for Tilera TILEPro chip.
;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
;; Contributed by Walter Lee (walt@tilera.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "tile")
; Make the scheduling automaton an ndfa.
(automata_option "ndfa")
; Name the three pipes.
(define_cpu_unit "X0" "tile")
(define_cpu_unit "X1" "tile")
(define_cpu_unit "Y0" "tile")
(define_cpu_unit "Y1" "tile")
(define_cpu_unit "Y2" "tile")
(define_insn_reservation "X0" 1
(eq_attr "type" "X0")
"X0")
(define_insn_reservation "X0_2cycle" 2
(eq_attr "type" "X0_2cycle")
"X0,nothing")
(define_insn_reservation "X1" 1
(eq_attr "type" "X1,X1_branch")
"X1")
(define_insn_reservation "X1_2cycle" 2
(eq_attr "type" "X1_2cycle")
"X1,nothing")
(define_insn_reservation "X1_L2" 8
(eq_attr "type" "X1_L2")
"X1")
(define_insn_reservation "X1_miss" 80
(eq_attr "type" "X1_miss")
"X1")
(define_insn_reservation "X01" 1
(eq_attr "type" "X01")
"X0|X1")
(define_insn_reservation "Y0" 1
(eq_attr "type" "Y0")
"Y0|X0")
(define_insn_reservation "Y0_2cycle" 2
(eq_attr "type" "Y0_2cycle")
"Y0|X0,nothing")
(define_insn_reservation "Y2" 1
(eq_attr "type" "Y2")
"Y2|X1")
(define_insn_reservation "Y2_2cycle" 2
(eq_attr "type" "Y2_2cycle")
"Y2|X1,nothing")
(define_insn_reservation "Y2_L2" 8
(eq_attr "type" "Y2_L2")
"Y2|X1")
(define_insn_reservation "Y2_miss" 80
(eq_attr "type" "Y2_miss")
"Y2|X1")
(define_insn_reservation "Y01" 1
(eq_attr "type" "Y01")
"Y0|Y1|X0|X1")
(define_insn_reservation "nothing" 0
(eq_attr "type" "nothing")
"nothing")
(define_insn_reservation "cannot_bundle" 1
(eq_attr "type" "cannot_bundle")
"X0+X1")
(define_insn_reservation "cannot_bundle_3cycle" 3
(eq_attr "type" "cannot_bundle_3cycle")
"X0+X1")
(define_insn_reservation "cannot_bundle_4cycle" 4
(eq_attr "type" "cannot_bundle_4cycle")
"X0+X1")
; A bundle must be in either X format or Y format.
(exclusion_set "X0,X1" "Y0,Y1,Y2")
|
