summaryrefslogtreecommitdiff
path: root/gcc/config/mips/mips-fixed.md
blob: fecb7ea706b9632e2eccaf0e528d56cc3df3a224 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
;; Copyright (C) 2007-2013 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.
;;
;; This file contains MIPS instructions that support fixed-point operations.

;; All supported fixed-point modes
(define_mode_iterator FIXED [(QQ "") (HQ "") (SQ "") (DQ "TARGET_64BIT")
			     (UQQ "") (UHQ "") (USQ "") (UDQ "TARGET_64BIT")
			     (HA "") (SA "") (DA "TARGET_64BIT")
			     (UHA "") (USA "") (UDA "TARGET_64BIT")])

;; For signed add/sub with saturation
(define_mode_iterator ADDSUB [(HQ "") (SQ "") (HA "") (SA "") (V2HQ "")
			      (V2HA "")])
(define_mode_attr addsubfmt [(HQ "ph") (SQ "w") (HA "ph") (SA "w")
			     (V2HQ "ph") (V2HA "ph")])

;; For unsigned add/sub with saturation
(define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2")
			       (UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP")
			       (V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")])
(define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph")
			      (V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")])

;; For signed multiplication with saturation
(define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP")
			    (SQ "ISA_HAS_DSPR2")])
(define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")])

(define_insn "add<mode>3"
  [(set (match_operand:FIXED 0 "register_operand" "=d")
	(plus:FIXED (match_operand:FIXED 1 "register_operand" "d")
		    (match_operand:FIXED 2 "register_operand" "d")))]
  ""
  "<d>addu\t%0,%1,%2"
  [(set_attr "type" "arith")
   (set_attr "mode" "<IMODE>")])

(define_insn "usadd<mode>3"
  [(parallel
    [(set (match_operand:UADDSUB 0 "register_operand" "=d")
	  (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
			   (match_operand:UADDSUB 2 "register_operand" "d")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
  ""
  "addu_s.<uaddsubfmt>\t%0,%1,%2"
  [(set_attr "type" "arith")
   (set_attr "mode" "<IMODE>")])

(define_insn "ssadd<mode>3"
  [(parallel
    [(set (match_operand:ADDSUB 0 "register_operand" "=d")
	  (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
			  (match_operand:ADDSUB 2 "register_operand" "d")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
  "ISA_HAS_DSP"
  "addq_s.<addsubfmt>\t%0,%1,%2"
  [(set_attr "type" "arith")
   (set_attr "mode" "<IMODE>")])

(define_insn "sub<mode>3"
  [(set (match_operand:FIXED 0 "register_operand" "=d")
        (minus:FIXED (match_operand:FIXED 1 "register_operand" "d")
		     (match_operand:FIXED 2 "register_operand" "d")))]
  ""
  "<d>subu\t%0,%1,%2"
  [(set_attr "type" "arith")
   (set_attr "mode" "<IMODE>")])

(define_insn "ussub<mode>3"
  [(parallel
    [(set (match_operand:UADDSUB 0 "register_operand" "=d")
	  (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
			    (match_operand:UADDSUB 2 "register_operand" "d")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
  ""
  "subu_s.<uaddsubfmt>\t%0,%1,%2"
  [(set_attr "type" "arith")
   (set_attr "mode" "<IMODE>")])

(define_insn "sssub<mode>3"
  [(parallel
    [(set (match_operand:ADDSUB 0 "register_operand" "=d")
	  (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
			   (match_operand:ADDSUB 2 "register_operand" "d")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
  "ISA_HAS_DSP"
  "subq_s.<addsubfmt>\t%0,%1,%2"
  [(set_attr "type" "arith")
   (set_attr "mode" "<IMODE>")])

(define_insn "ssmul<mode>3"
  [(parallel
    [(set (match_operand:MULQ 0 "register_operand" "=d")
          (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
			(match_operand:MULQ 2 "register_operand" "d")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
     (clobber (match_scratch:DI 3 "=x"))])]
  ""
  "mulq_rs.<mulqfmt>\t%0,%1,%2"
  [(set_attr "type"     "imul3")
   (set_attr "mode"     "<IMODE>")])

(define_insn "ssmaddsqdq4"
  [(parallel
    [(set (match_operand:DQ 0 "register_operand" "=a")
	  (ss_plus:DQ
	  (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
				     "register_operand" "d"))
                      (sat_fract:DQ (match_operand:SQ 2
				     "register_operand" "d")))
          (match_operand:DQ 3 "register_operand" "0")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_DPAQ_SA_L_W))])]
  "ISA_HAS_DSP && !TARGET_64BIT"
  "dpaq_sa.l.w\t%q0,%1,%2"
  [(set_attr "type" "imadd")
   (set_attr "mode" "SI")])

(define_insn "ssmsubsqdq4"
  [(parallel
    [(set (match_operand:DQ 0 "register_operand" "=a")
          (ss_minus:DQ
	   (match_operand:DQ 3 "register_operand" "0")
           (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
				      "register_operand" "d"))
                       (sat_fract:DQ (match_operand:SQ 2
				      "register_operand" "d")))))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_DPSQ_SA_L_W))])]
  "ISA_HAS_DSP && !TARGET_64BIT"
  "dpsq_sa.l.w\t%q0,%1,%2"
  [(set_attr "type" "imadd")
   (set_attr "mode" "SI")])