1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
|
;; Generic ARM Pipeline Description
;; Copyright (C) 2003-2013 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
(define_automaton "arm")
;; Write buffer
;
; Strictly, we should model a 4-deep write buffer for ARM7xx based chips
;
; The write buffer on some of the arm6 processors is hard to model exactly.
; There is room in the buffer for up to two addresses and up to eight words
; of memory, but the two needn't be split evenly. When writing the two
; addresses are fully pipelined. However, a read from memory that is not
; currently in the cache will block until the writes have completed.
; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so
; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous
; (they aren't allowed to be at present) then there is a startup cost of 1MCLK
; cycle to add as well.
(define_cpu_unit "write_buf" "arm")
;; Write blockage unit
;
; The write_blockage unit models (partially), the fact that reads will stall
; until the write buffer empties.
(define_cpu_unit "write_blockage" "arm")
;; Core
;
(define_cpu_unit "core" "arm")
(define_insn_reservation "store_wbuf" 5
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "yes")
(eq_attr "type" "store1")))
"core+write_buf*3+write_blockage*5")
(define_insn_reservation "store2_wbuf" 7
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "yes")
(eq_attr "type" "store2")))
"core+write_buf*4+write_blockage*7")
(define_insn_reservation "store3_wbuf" 9
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "yes")
(eq_attr "type" "store3")))
"core+write_buf*5+write_blockage*9")
(define_insn_reservation "store4_wbuf" 11
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "yes")
(eq_attr "type" "store4")))
"core+write_buf*6+write_blockage*11")
(define_insn_reservation "store2" 3
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "no")
(eq_attr "type" "store2")))
"core*3")
(define_insn_reservation "store3" 4
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "no")
(eq_attr "type" "store3")))
"core*4")
(define_insn_reservation "store4" 5
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "no")
(eq_attr "type" "store4")))
"core*5")
(define_insn_reservation "store_ldsched" 1
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "yes")
(eq_attr "type" "store1")))
"core")
(define_insn_reservation "load_ldsched_xscale" 3
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "yes")
(and (eq_attr "type" "load_byte,load1")
(eq_attr "tune" "xscale,iwmmxt,iwmmxt2"))))
"core")
(define_insn_reservation "load_ldsched" 2
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "yes")
(and (eq_attr "type" "load_byte,load1")
(eq_attr "tune" "!xscale,iwmmxt,iwmmxt2"))))
"core")
(define_insn_reservation "load_or_store" 2
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "!yes")
(eq_attr "type" "load_byte,load1,load2,load3,load4,store1")))
"core*2")
(define_insn_reservation "mult" 16
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "no")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))
"core*16")
(define_insn_reservation "mult_ldsched_strongarm" 3
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "yes")
(and (eq_attr "tune"
"strongarm,strongarm110,strongarm1100,strongarm1110")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))))
"core*2")
(define_insn_reservation "mult_ldsched" 4
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "yes")
(and (eq_attr "tune"
"!strongarm,strongarm110,strongarm1100,strongarm1110")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))))
"core*4")
(define_insn_reservation "multi_cycle" 32
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "core_cycles" "multi")
(and (eq_attr "type" "!load_byte,load1,load2,load3,load4,\
store1,store2,store3,store4")
(not (ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))))
"core*32")
(define_insn_reservation "single_cycle" 1
(and (eq_attr "generic_sched" "yes")
(eq_attr "core_cycles" "single"))
"core")
|
