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2013-03-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/56720
* gcc.target/arm/neon-vcond-gt.c: New test.
* gcc.target/arm/neon-vcond-ltgt.c: Likewise.
* gcc.target/arm/neon-vcond-unordered.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197041 138bc75d-0d04-0410-961f-82ee72b054a4
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PR target/56720
* config/arm/iterators.md (v_cmp_result): New mode attribute.
* config/arm/neon.md (vcond<mode><mode>): Handle unordered cases.
2013-03-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/56720
* gcc.target/arm/neon-vcond-gt.c: New test.
* gcc.target/arm/neon-vcond-ltgt.c: Likewise.
* gcc.target/arm/neon-vcond-unordered.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197040 138bc75d-0d04-0410-961f-82ee72b054a4
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PR tree-optimization/56689
* tree-vrp.c (execute_vrp): Mark loops for fixup if we removed
any edge.
* gcc.dg/torture/pr56689.c: New testcase.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197039 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197034 138bc75d-0d04-0410-961f-82ee72b054a4
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PR fortran/56696
* io/list_read.c (read_real): Fix EOF diagnostic.
2013-03-24 Tobias Burnus <burnus@net-b.de>
PR fortran/56696
* gfortran.dg/eof_5.f90: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197019 138bc75d-0d04-0410-961f-82ee72b054a4
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* gcc.c-torture/execute/builtins/builtins.exp: Sort targets
alphabetically.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197007 138bc75d-0d04-0410-961f-82ee72b054a4
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* pt.c (instantiation_dependent_r): Check DECL_INITIAL of VAR_DECL
and CONST_DECL.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196983 138bc75d-0d04-0410-961f-82ee72b054a4
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*mov<mode>_internal_rex64. Use x64 and nox64 isa attributes.
Emit insn template depending on type attribute. Use
HAVE_AS_IX86_INTERUNIT_MOVQ to handle broken assemblers that require
movd instead of movq mnemonic for interunit moves. Rewrite mode
attribute calculation. Remove unit attribute calculation.
Set prefix attribute to maybe_vex for sselog1 and ssemov types.
Set prefix_data16 attribute for DImode ssemov types.
Use Ym instead of y for SSE-MMX conversion alternatives.
Reorder operand constraints.
testsuite/ChangeLog:
* gcc.target/i386/pr22152.c (dg-options): Add -mtune=core2.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196981 138bc75d-0d04-0410-961f-82ee72b054a4
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PR testsuite/55994
* gcc.c-torture/execute/builtins/builtins.exp: Add
-Wl,--allow-multiple-definition for RTEMS targets.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196970 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196958 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196957 138bc75d-0d04-0410-961f-82ee72b054a4
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gcc/
* tree.h (VECTOR_TYPE_P): New macro.
(VECTOR_INTEGER_TYPE_P, VECTOR_FLOAT_TYPE_P, FLOAT_TYPE_P,
TYPE_MODE): Use it.
* fold-const.c (fold_cond_expr_with_comparison): Use build_zero_cst.
VEC_COND_EXPR cannot be lvalues.
(fold_ternary_loc) <VEC_COND_EXPR>: Merge with the COND_EXPR case.
gcc/cp/
* call.c (build_conditional_expr_1): Fold VEC_COND_EXPR.
gcc/testsuite/
* g++.dg/ext/vector21.C: New testcase.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196884 138bc75d-0d04-0410-961f-82ee72b054a4
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2013-03-21 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/arm-protos.h (tune_params): Add
prefer_neon_for_64bits field.
* config/arm/arm.c (prefer_neon_for_64bits): New variable.
(arm_slowmul_tune): Default prefer_neon_for_64bits to false.
(arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto.
(arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto.
(arm_cortex_a15_tune, arm_cortex_a5_tune): Ditto.
(arm_cortex_a9_tune, arm_v6m_tune, arm_fa726te_tune): Ditto.
(arm_option_override): Handle -mneon-for-64bits new option.
* config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro.
(prefer_neon_for_64bits): Declare new variable.
* config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to
avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and
nota8.
(arch_enabled): Handle new arch types. Remove support for onlya8
and nota8.
(one_cmpldi2): Use new arch names.
* config/arm/arm.opt (mneon-for-64bits): Add option.
* config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon)
(anddi3_neon, xordi3_neon, ashldi3_neon, <shift>di3_neon): Use
neon_for_64bits instead of nota8 and avoid_neon_for_64bits instead
of onlya8.
* doc/invoke.texi (-mneon-for-64bits): Document.
gcc/testsuite:
* gcc.target/arm/neon-for-64bits-1.c: New tests.
* gcc.target/arm/neon-for-64bits-2.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196876 138bc75d-0d04-0410-961f-82ee72b054a4
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* tree-vect-data-refs.c (vect_update_interleaving_chain): Remove.
(vect_insert_into_interleaving_chain): Likewise.
(vect_drs_dependent_in_basic_block): Inline ...
(vect_slp_analyze_data_ref_dependence): ... here. New function,
split out from ...
(vect_analyze_data_ref_dependence): ... here. Simplify.
(vect_check_interleaving): Simplify.
(vect_analyze_data_ref_dependences): Likewise. Split out ...
(vect_slp_analyze_data_ref_dependences): ... this new function.
(dr_group_sort_cmp): New function.
(vect_analyze_data_ref_accesses): Compute data-reference groups
here instead of in vect_analyze_data_ref_dependence. Use
a more efficient algorithm.
* tree-vect-slp.c (vect_slp_analyze_bb_1): Use
vect_slp_analyze_data_ref_dependences. Call
vect_analyze_data_ref_accesses earlier.
* tree-vect-loop.c (vect_analyze_loop_2): Likewise.
* tree-vectorizer.h (vect_analyze_data_ref_dependences): Adjust.
(vect_slp_analyze_data_ref_dependences): New prototype.
* gcc.dg/vect/vect-outer-3a-big-array.c: Adjust.
* gcc.dg/vect/vect-outer-3a.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196872 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/aarch64/aarch64-simd.md (simd_fabd): New Attribute.
(abd<mode>_3): New pattern.
(aba<mode>_3): New pattern.
(fabd<mode>_3): New pattern.
2013-03-21 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gcc.target/aarch64/vect.c: Test and result vector added
for sabd and saba instructions.
* gcc.target/aarch64/vect-compile.c: Check for sabd and saba
instructions in assembly.
* gcc.target/aarch64/vect.x: Add sabd and saba test functions.
* gcc.target/aarch64/vect-fp.c: Test and result vector added
for fabd instruction.
* gcc.target/aarch64/vect-fp-compile.c: Check for fabd
instruction in assembly.
* gcc.target/aarch64/vect-fp.x: Add fabd test function.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196858 138bc75d-0d04-0410-961f-82ee72b054a4
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addititional equivalences for equality comparisons between an SSA_NAME
and a constant where the SSA_NAME was set from a widening conversion.
* g++.dg/tree-ssa/ssa-dom.C: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196855 138bc75d-0d04-0410-961f-82ee72b054a4
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* parser.c (cp_parser_late_return_type_opt): Save and restore
current_class_ptr/ref.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196853 138bc75d-0d04-0410-961f-82ee72b054a4
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* expr.c (cplus_expand_constant): Do nothing if the class is
incomplete.
* semantics.c (reduced_constant_expression_p): Allow PTRMEM_CST.
* typeck2.c (store_init_value): Use reduced_constant_expression_p.
* decl.c (maybe_register_incomplete_var): Handle PTRMEM_CST.
(complete_vars): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196852 138bc75d-0d04-0410-961f-82ee72b054a4
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get_file_function_name.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196851 138bc75d-0d04-0410-961f-82ee72b054a4
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PR c++/56642
* pt.c (tsubst_decl): Check return value of register_specialization.
* typeck2.c (abstract_virtuals_error_sfinae): Re-apply complete_type
change.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196849 138bc75d-0d04-0410-961f-82ee72b054a4
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2013-03-20 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/predicates.md (indexed_address, update_address_mem
update_indexed_address_mem): New predicates.
* config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type"
attribute for load/store instructions.
* config/rs6000/dfp.md (movsd_store): Likewise.
(movsd_load): Likewise.
* config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise.
(unnamed HI->DI extend define_insn): Likewise.
(unnamed SI->DI extend define_insn): Likewise.
(unnamed QI->SI extend define_insn): Likewise.
(unnamed QI->HI extend define_insn): Likewise.
(unnamed HI->SI extend define_insn): Likewise.
(unnamed HI->SI extend define_insn): Likewise.
(extendsfdf2_fpr): Likewise.
(movsi_internal1): Likewise.
(movsi_internal1_single): Likewise.
(movhi_internal): Likewise.
(movqi_internal): Likewise.
(movcc_internal1): Correct mnemonic for stw insn. Set correct "type"
attribute for load/store instructions.
(mov<mode>_hardfloat): Set correct "type" attribute for load/store
instructions.
(mov<mode>_softfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat64): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
(probe_stack_<mode>): Likewise.
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary
floating point, and decimal floating point to reload iterator.
* config/rs6000/constraints.md (wl constraint): New constraints to
return FLOAT_REGS if certain options are used to reduce the number
of separate patterns that exist in the file.
(wx constraint): Likewise.
(wz constraint): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro,
define as 1 if we are running on a power7 or newer.
(enum r6000_reg_class_enum): Add new constraints.
* config/rs6000/dfp.md (movsd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7. Use xxlxor to create
0.0f.
(movsd splitter): Likewise.
(movsd_hardfloat): Likewise.
(movsd_softfloat): Likewise.
* config/rs6000/rs6000.md (FMOVE32): New iterators to combine
binary and decimal floating point moves.
(fmove_ok): New attributes to combine binary and decimal floating
point moves, and to combine power6x (mfpgpr) moves along normal
floating moves.
(real_value_to_target): Likewise.
(f32_lr): Likewise.
(f32_lm): Likewise.
(f32_li): Likewise.
(f32_sr): Likewise.
(f32_sm): Likewise.
(f32_si): Likewise.
(movsf): Combine binary and decimal floating point moves. Combine
power6x (mfpgpr) moves with other moves by using conditional
constraits (wg). Use LFIWZX and STFIWX for loading SDmode on
power7.
(mov<mode> for SFmode/SDmode); Likewise.
(SFmode/SDmode splitters): Likewise.
(movsf_hardfloat): Likewise.
(mov<mode>_hardfloat for SFmode/SDmode): Likewise.
(movsf_softfloat): Likewise.
(mov<mode>_softfloat for SFmode/SDmode): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl,
wx and wz constraints.
* config/rs6000/constraints.md (wg constraint): New constraint to
return FLOAT_REGS if -mmfpgpr (power6x) was used.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/dfp.md (movdd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7.
(movdd splitters): Likewise.
(movdd_hardfloat32): Likewise.
(movdd_softfloat32): Likewise.
(movdd_hardfloat64_mfpgpr): Likewise.
(movdd_hardfloat64): Likewise.
(movdd_softfloat64): Likewise.
* config/rs6000/rs6000.md (FMOVE64): New iterators to combine
64-bit binary and decimal floating point moves.
(FMOVE64X): Likewise.
(movdf): Combine 64-bit binary and decimal floating point moves.
Combine power6x (mfpgpr) moves with other moves by using
conditional constraits (wg).
(mov<mode> for DFmode/DDmode): Likewise.
(DFmode/DDmode splitters): Likewise.
(movdf_hardfloat32): Likewise.
(mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.
(movdf_softfloat32): Likewise.
(movdf_hardfloat64_mfpgpr): Likewise.
(movdf_hardfloat64): Likewise.
(mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.
(movdf_softfloat64): Likewise.
(mov<mode>_softfloat64 for DFmode/DDmode): Likewise.
(reload_<mode>_load): Move to later in the file so they aren't in
the middle of the floating point move insns.
(reload_<mode>_store): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg
constraint if -mdebug=reg.
(rs6000_initi_hard_regno_mode_ok): Enable wg constraint if
-mfpgpr. Enable using dd reload support if needed.
* config/rs6000/dfp.md (movtd): Delete, combine with 128-bit
binary and decimal floating point moves in rs6000.md.
(movtd_internal): Likewise.
* config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and
decimal floating point moves.
(movtf): Likewise.
(movtf_internal): Likewise.
(mov<mode>_internal, TDmode/TFmode): Likewise.
(movtf_softfloat): Likewise.
(mov<mode>_softfloat, TDmode/TFmode): Likewise.
* config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with
movdi_internal64, using wg constraint for move direct operations.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print
MODES_TIEABLE_P for selected modes. Print the numerical value of
the various virtual registers. Use GPR/FPR first/last values,
instead of hard coding the register numbers. Print which modes
have reload functions registered.
(rs6000_option_override_internal): If -mdebug=reg, trace the
options settings before/after setting cpu, target and subtarget
settings.
(rs6000_secondary_reload_trace): Improve the RTL dump for
-mdebug=addr and for secondary reload failures in
rs6000_secondary_reload_inner.
(rs6000_secondary_reload_fail): Likewise.
(rs6000_secondary_reload_inner): Likewise.
* config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience
macros for first/last GPR and FPR registers.
(LAST_GPR_REGNO): Likewise.
(FIRST_FPR_REGNO): Likewise.
(LAST_FPR_REGNO): Likewise.
* config/rs6000/vector.md (mul<mode>3): Use the combined macro
VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to
VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.
(vcond<mode><mode>): Likewise.
(vcondu<mode><mode>): Likewise.
(vector_gtu<mode>): Likewise.
(vector_gte<mode>): Likewise.
(xor<mode>3): Don't allow logical operations on TImode in 32-bit
to prevent the compiler from converting DImode operations to
TImode.
(ior<mode>3): Likewise.
(and<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(nor<mode>3): Likewise.
(andc<mode>3): Likewise.
* config/rs6000/constraints.md (wt constraint): New constraint
that returns VSX_REGS if TImode is allowed in VSX registers.
* config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy
constant under VSX.
* config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is
similar to TImode, but it is restricted to being in the GPRs.
* config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow
TImode to occupy a single VSX register.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to
-mvsx-timode for power7/power8.
(power7 cpu): Likewise.
(power8 cpu): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make
sure that TFmode/TDmode take up two registers if they are ever
allowed in the upper VSX registers.
(rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX
registers.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_debug_reg_global): Add debugging for PTImode and wt
constraint. Print if LRA is turned on.
(rs6000_option_override_internal): Give an error if -mvsx-timode
and VSX is not enabled.
(invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If
-mvsx-timode, restrict TImode to reg+reg addressing, and PTImode
to reg+offset addressing. Use PTImode when checking offset
addresses for validity.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Likewise.
(rs6000_eliminate_indexed_memrefs): Likewise.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload): Likewise.
(rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit
reloads to fpr registers to continue to use reg+offset addressing,
but 64-bit reloads to altivec registers need reg+reg addressing.
Drop test for PRE_MODIFY, since VSX loads/stores no longer support
it. Treat LO_SUM like a PLUS operation.
(rs6000_secondary_reload_class): If type is 64-bit, prefer to use
FLOAT_REGS instead of VSX_RGS to allow use of reg+offset
addressing.
(rs6000_cannot_change_mode_class): Do not allow TImode in VSX
registers to share a register with a smaller sized type, since VSX
puts scalars in the upper 64-bits.
(print_operand): Add support for PTImode.
(rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of
VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX
registers, but don't have arithmetic support.
(rs6000_memory_move_cost): Add test for VSX.
(rs6000_opt_masks): Add -mvsx-timode.
* config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves
for TImode.
(VSs): Likewise.
(VSr): Use wt constraint for TImode.
(VSv): Drop TImode support.
(vsx_movti): Delete, replace with versions for 32-bit and 64-bit.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
(vec_store_<mode>): Use VSX iterator instead of vector iterator.
(vsx_and<mode>3): Delete use of '?' constraint on inputs, just put
one '?' on the appropriate output constraint. Do not allow TImode
logical operations on 32-bit systems.
(vsx_ior<mode>3): Likewise.
(vsx_xor<mode>3): Likewise.
(vsx_one_cmpl<mode>2): Likewise.
(vsx_nor<mode>3): Likewise.
(vsx_andc<mode>3): Likewise.
(vsx_concat_<mode>): Likewise.
(vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.
* config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from
OPTION_MASK_VSX_TIMODE.
(enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(STACK_SAVEAREA_MODE): Use PTImode instead of TImode.
* config/rs6000/rs6000.md (INT mode attribute): Add PTImode.
(TI2 iterator): New iterator for TImode, PTImode.
(wd mode attribute): Add values for vector types.
(movti_string): Replace TI move operations with operations for
TImode and PTImode. Add support for TImode being allowed in VSX
registers.
(mov<mode>_string, TImode/PTImode): Likewise.
(movti_ppc64): Likewise.
(mov<mode>_ppc64, TImode/PTImode): Likewise.
(TI mode splitters): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt
constraint.
[gcc/testsuite]
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/mmfpgpr.c: New test.
* gcc.target/powerpc/sd-vsx.c: Likewise.
* gcc.target/powerpc/sd-pwr6.c: Likewise.
* gcc.target/powerpc/vsx-float0.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196831 138bc75d-0d04-0410-961f-82ee72b054a4
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PR tree-optimization/56355
gcc/
* fold-const.c (tree_binary_nonnegative_warnv_p) <MULT_EXPR>:
Also handle integers with undefined overflow.
gcc/testsuite/
* gcc.dg/pr56355-1.c: New file.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196829 138bc75d-0d04-0410-961f-82ee72b054a4
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2013-03-20 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Tom de Vries <tom@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
Iain Sandoe <iain@codesourcery.com>
Nathan Froyd <froydnj@codesourcery.com>
Chao-ying Fu <fu@mips.com>
* doc/extend.texi: (micromips, nomicromips, nocompression):
Document new function attributes.
* doc/invoke.texi (minterlink-compressed, mmicromips,
m14k, m14ke, m14kec): Document new options.
(minterlink-mips16): Update documentation.
* doc/md.texi (ZC, ZD): Document new constraints.
* configure.ac (gcc_cv_as_micromips): Check if linker
supports the .set micromips directive.
* configure: Regenerate.
* config.in: Regenerate.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/micromips.md: New file.
* constraints.md (ZC, ZD): New constraints.
* config/mips/predicates.md (movep_src_register): New predicate.
(movep_src_operand): New predicate.
(non_volatile_mem_operand): New predicate.
* config/mips/mips.md (multimem): New type.
(length): Differentiate between 17-bit and 18-bit branch offsets.
(MOVEP1, MOVEP2): New mode iterator.
(mov_<load>l): Use ZC constraint.
(mov_<load>r): Likewise.
(mov_<store>l): Likewise.
(mov_<store>r): Likewise.
(*branch_equality<mode>_inverted): Add microMIPS support.
(*branch_equality<mode>): Likewise.
(*jump_absolute): Likewise.
(indirect_jump_<mode>): Likewise.
(tablejump_<mode>): Likewise.
(<optab>_internal): Likewise.
(sibcall_internal): Likewise.
(sibcall_value_internal): Likewise.
(prefetch): Use constraint ZD.
* config/mips/mips.opt (minterlink-compressed): New option.
(minterlink-mips16): Now an alias for minterlink-compressed.
(mmicromips): New option.
* config/mips/sync.md (sync_compare_and_swap<mode>): Use ZR constraint.
(compare_and_swap_12): Likewise.
(sync_add<mode>): Likewise.
(sync_<optab>_12): Likewise.
(sync_old_<optab>_12): Likewise.
(sync_new_<optab>_12): Likewise.
(sync_nand_12): Likewise.
(sync_old_nand_12): Likewise.
(sync_new_nand_12): Likewise.
(sync_sub<mode>): Likewise.
(sync_old_add<mode>): Likewise.
(sync_old_sub<mode>): Likewise.
(sync_new_add<mode>): Likewise.
(sync_new_sub<mode>): Likewise.
(sync_<optab><mode>): Likewise.
(sync_old_<optab><mode>): Likewise.
(sync_new_<optab><mode>): Likewise.
(sync_nand<mode>): Likewise.
(sync_old_nand<mode>): Likewise.
(sync_new_nand<mode>): Likewise.
(sync_lock_test_and_set<mode>): Likewise.
(test_and_set_12): Likewise.
(atomic_compare_and_swap<mode>): Likewise.
(atomic_exchange<mode>_llsc): Likewise.
(atomic_fetch_add<mode>_llsc): Likewise.
* config/mips/mips-cpus.def (m14kc, m14k): New processors.
* config/mips/mips-protos.h (umips_output_save_restore): New prototype.
(umips_save_restore_pattern_p): Likewise.
(umips_load_store_pair_p): Likewise.
(umips_output_load_store_pair): Likewise.
(umips_movep_target_p): Likewise.
(umips_12bit_offset_address_p): Likewise.
* config/mips/mips.c (MIPS_MAX_FIRST_STEP): Update for microMIPS.
(mips_base_mips16): Rename this...
(mips_base_compression_flags): ...to this. Update all uses.
(mips_attribute_table): Add micromips, nomicromips and nocompression.
(mips_mips16_decl_p): Delete.
(mips_nomips16_decl_p): Delete.
(mips_get_compress_on_flags): New function.
(mips_get_compress_off_flags): New function.
(mips_get_compress_mode): New function.
(mips_get_compress_on_name): New function.
(mips_get_compress_off_name): New function.
(mips_insert_attributes): Support multiple compression types.
(mips_merge_decl_attributes): Likewise.
(umips_12bit_offset_address_p): New function.
(mips_start_function_definition): Emit .set micromips directive.
(mips_call_may_need_jalx_p): New function.
(mips_function_ok_for_sibcall): Add microMIPS support.
(mips_print_operand_punctuation): Support short delay slots and
compact jumps.
(umips_swm_mask, umips_swm_encoding): New.
(umips_build_save_restore): New function.
(mips_for_each_saved_gpr_and_fpr): Add microMIPS support.
(was_mips16_p): Remove.
(old_compression_mode): New.
(mips_set_compression_mode): New function.
(mips_set_current_function): Add microMIPS support.
(mips_option_override): Likewise.
(umips_save_restore_pattern_p): New function.
(umips_output_save_restore): New function.
(umips_load_store_pair_p_1): New function.
(umips_load_store_pair_p): New function.
(umips_output_load_store_pair_1): New function.
(umips_output_load_store_pair): New function.
(umips_movep_target_p) New function.
(mips_prepare_pch_save): Add microMIPS support.
* config/mips/mips.h (TARGET_COMPRESSION): New.
(TARGET_CPU_CPP_BUILTINS): Update macro
to use new compression flags and to support microMIPS.
(MIPS_ISA_LEVEL_SPEC): Add m14k processors.
(MIPS_ARCH_FLOAT_SPEC): Likewise.
(ISA_HAS_LWXS): Include TARGET_MICROMIPS.
(ISA_HAS_LOAD_DELAY): Exclude TARGET_MICROMIPS.
(ASM_SPEC): Support mmicromips and mno-micromips.
(M16STORE_REG_P): New macro.
(MIPS_CALL): Support TARGET_MICROMIPS.
(MICROMIPS_J): New macro.
(mips_base_mips16): Rename this...
(mips_base_compression_flags): ...to this.
(UMIPS_12BIT_OFFSET_P): New macro.
* config/mips/t-sde: (MULTILIB_OPTIONS): Add microMIPS.
(MULTILIB_DIRNAMES): Likewise.
libgcc/
2013-03-20 Catherine Moore <clm@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Chao-ying Fu <fu@mips.com>
* config/mips/mips16.S: Don't build for microMIPS.
* config/mips/linux-unwind.h: Handle microMIPS frame.
* config/mips/crtn.S (fini, init): New labels.
gcc/testsuite/
2013-03-20 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gcc.target/mips/mips.exp: Add microMIPS support.
* gcc.target/mips/umips-movep-2.c: New test.
* gcc.target/mips/umips-lwp-2.c: New test.
* gcc.target/mips/umips-swp-5.c: New test.
* gcc.target/mips/umips-constraints-1.c: New test.
* gcc.target/mips/umips-lwp-3.c: New test.
* gcc.target/mips/umips-swp-6.c: New test.
* gcc.target/mips/umips-constraints-2.c: New test.
* gcc.target/mips/umips-save-restore-1.c: New test.
* gcc.target/mips/umips-lwp-4.c: New test.
* gcc.target/mips/umips-swp-7.c: New test.
* gcc.target/mips/umips-save-restore-2.c: New test.
* gcc.target/mips/umips-lwp-swp-volatile.c: New test.
* gcc.target/mips/umips-lwp-5.c: New test.
* gcc.target/mips/umips-save-restore-3.c: New test.
* gcc.target/mips/umips-lwp-6.c: New test.
* gcc.target/mips/umips-swp-1.c: New test.
* gcc.target/mips/umips-lwp-7.c: New test.
* gcc.target/mips/umips-swp-2.c: New test.
* gcc.target/mips/umips-lwp-8.c: New test.
* gcc.target/mips/umips-swp-3.c: New test.
* gcc.target/mips/umips-movep-1.c: New test.
* gcc.target/mips/umips-lwp-1.c: New test.
* gcc.target/mips/umips-swp-4.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196828 138bc75d-0d04-0410-961f-82ee72b054a4
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PR tree-optimization/56661
* tree-ssa-sccvn.c (visit_use): Only value-number calls if
the result does not have to be distinct.
* gcc.dg/torture/pr56661.c: New testcase.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196825 138bc75d-0d04-0410-961f-82ee72b054a4
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2013-03-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Steven Bosscher <steven@gcc.gnu.org>
PR rtl-optimization/56605
* loop-iv.c (implies_p): Handle equal RTXs and subregs.
gcc/testsuite:
2013-03-13 Bill Schmidt wschmidt@linux.vnet.ibm.com>
PR rtl-optimization/56605
* gcc.target/powerpc/pr56605.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196823 138bc75d-0d04-0410-961f-82ee72b054a4
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PR fortran/54932
* gfortran.dg/do_1.f90: Don't xfail.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196821 138bc75d-0d04-0410-961f-82ee72b054a4
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PR libfortran/51825
* io/list_read.c (nml_read_obj): Don't end the component loop on
a nested derived type, but continue with the next loop iteration.
(nml_get_obj_data): Don't move the first_nl pointer further in
the list if a qualifier was found.
2013-03-20 Tilo Schwarz <tilo@tilo-schwarz.de>
PR libfortran/51825
* gcc/testsuite/gfortran.dg/namelist_77.f90: New.
* gcc/testsuite/gfortran.dg/namelist_78.f90: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196806 138bc75d-0d04-0410-961f-82ee72b054a4
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PR libfortran/48618
* io/open.c (st_open): Raise error for unit number < 0 only if
unit number does not exist already.
2013-03-20 Tilo Schwarz <tilo@tilo-schwarz.de>
PR libfortran/48618
* gfortran.dg/open_negative_unit_1.f90: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196805 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196797 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196796 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196795 138bc75d-0d04-0410-961f-82ee72b054a4
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PR tree-optimization/56273
* passes.c (init_optimization_passes): Move second VRP after DOM.
* gcc.dg/tree-ssa/vrp47.c: Adjust.
* c-c++-common/uninit-17.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196792 138bc75d-0d04-0410-961f-82ee72b054a4
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filenames.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196790 138bc75d-0d04-0410-961f-82ee72b054a4
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* fold-const.c (operand_equal_p): For MEM_REF and TARGET_MEM_REF,
require types_compatible_p types.
* g++.dg/torture/pr56635.C: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196781 138bc75d-0d04-0410-961f-82ee72b054a4
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PR tree-optimization/3713
* tree-ssa-sccvn.c (visit_copy): Simplify. Always propagate
has_constants and expr.
(stmt_has_constants): Properly valueize SSA names when deciding
whether the stmt has constants.
* g++.dg/ipa/devirt-12.C: New testcase.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196771 138bc75d-0d04-0410-961f-82ee72b054a4
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* tree.c (tree_int_cst_min_precision): For integer_zerop (value)
return 1 even for !unsignedp.
* c-c++-common/pr56566.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196767 138bc75d-0d04-0410-961f-82ee72b054a4
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PR c++/56639
* parser.c (cp_parser_direct_declarator): Bail if we see a
qualified-id not at namespace scope.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196765 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196764 138bc75d-0d04-0410-961f-82ee72b054a4
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* cp-tree.h (WILDCARD_TYPE_P): Split out from...
(MAYBE_CLASS_TYPE_P): ...here.
* semantics.c (lambda_capture_field_type): Only build a
magic decltype for wildcard types.
(lambda_proxy_type): Likewise.
(finish_non_static_data_member): Get the quals from
the object.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196747 138bc75d-0d04-0410-961f-82ee72b054a4
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* parser.c (cp_parser_template_argument): Don't
fold_non_dependent_expr.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196746 138bc75d-0d04-0410-961f-82ee72b054a4
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* parser.c (cp_parser_template_id): Don't forget access checks.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196744 138bc75d-0d04-0410-961f-82ee72b054a4
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* pt.c (tsubst_qualified_id): Use current_nonlambda_class_type.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196743 138bc75d-0d04-0410-961f-82ee72b054a4
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PR c++/55972
* name-lookup.h (tag_scope): Add ts_lambda.
* semantics.c (begin_lambda_type): Use it.
* decl.c (xref_tag_1): Set CLASSTYPE_LAMBDA_EXPR.
* pt.c (check_default_tmpl_args): Ignore lambdas.
(push_template_decl_real): Handle lambdas.
* tree.c (no_linkage_check): Adjust lambda check.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196742 138bc75d-0d04-0410-961f-82ee72b054a4
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* tree.c (strip_typedefs_expr): Complain about lambda, don't abort.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196741 138bc75d-0d04-0410-961f-82ee72b054a4
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* parser.c (cp_parser_direct_declarator): Fix late return
for out-of-class defn of member function.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196740 138bc75d-0d04-0410-961f-82ee72b054a4
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* semantics.c (maybe_add_lambda_conv_op): Clear DECL_NAME of copied
parms to avoid duplicate -Wshadow warnings.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196739 138bc75d-0d04-0410-961f-82ee72b054a4
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PR c++/52748
* cp-tree.h (tsubst_flags): Add tf_decltype.
* call.c (build_cxx_call): Don't build a temporary if it's set.
(build_over_call): Make sure it's only passed to build_cxx_call.
* parser.c (cp_parser_primary_expression): Add decltype_p parm.
(cp_parser_unary_expression): Likewise.
(cp_parser_cast_expression): Likewise.
(cp_parser_binary_expression): Likewise.
(cp_parser_assignment_expression): Likewise.
(cp_parser_postfix_expression): Likewise. Pass tf_decltype.
(cp_parser_explicit_instantiation): Add decltype_p. Force a
temporary for a call on the LHS of a comma.
(cp_parser_decltype): Pass true to decltype_p parms.
* pt.c (tsubst) [DECLTYPE_TYPE]: Pass tf_decltype.
(tsubst_copy_and_build): Pass tf_decltype down only for
CALL_EXPR and the RHS of COMPOUND_EXPR.
* tree.c (build_cplus_new): Call complete_type_or_maybe_complain.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196736 138bc75d-0d04-0410-961f-82ee72b054a4
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* typeck2.c (pending_abstract_type): Add use field.
(abstract_virtuals_error_sfinae): Add overloads taking
abstract_class_use instead of tree.
* typeck.c (build_static_cast_1): Call it.
* except.c (is_admissible_throw_operand_or_catch_parameter): Call it.
* pt.c: Adjust calls.
* decl.c (cp_finish_decl): Don't handle functions specially.
(grokdeclarator): Always check return type.
* init.c (build_new_1): Adjust call.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196735 138bc75d-0d04-0410-961f-82ee72b054a4
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PR c++/17232
* pt.c (tsubst) [ARRAY_TYPE]: Use abstract_virtuals_error_sfinae.
* typeck2.c (abstract_virtuals_error_sfinae): Call complete_type.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196734 138bc75d-0d04-0410-961f-82ee72b054a4
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* pt.c (tsubst_function_type): Call abstract_virtuals_error_sfinae.
(tsubst_arg_types): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196733 138bc75d-0d04-0410-961f-82ee72b054a4
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