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* Extend STV pass to 64-bit modehjl/pr70155/masterH.J. Lu2016-04-261-37/+374
* i386: Add a variant peephole for lea rather than ops that clobber CC.bernds2016-04-261-0/+32
* Support .largecomm with Solaris as (PR target/61821)ro2016-04-264-11/+23
* Support .lbss etc. sections with Solaris as (PR target/59407)ro2016-04-262-2/+16
* * config/i386/i386.md (*movxi_internal_avx512f): Use insn typeuros2016-04-252-13/+15
* * config/i386/predicates.md (const0_operand): Do not matchuros2016-04-251-2/+2
* * config/i386/i386.md (*movoi_internal_avx): Set mode attribute to XIuros2016-04-254-28/+36
* 2016-04-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>wschmidt2016-04-251-7/+7
* * config/msp430/msp430.md (ashlhi3): Optimize one bit shifts.nickc2016-04-251-0/+9
* 2016-04-25 Michael Collison <michael.collison@linaro.org>collison2016-04-254-52/+201
* * config/i386/i386.md (*lea<mode>_general_4): Use const_0_to_3_operanduros2016-04-241-7/+5
* * config/i386/i386-protos.h (standard_sse_constant_p): Adduros2016-04-246-102/+151
* [PATCH 2/2] (header usage fix) include c++ headers in system.hnsz2016-04-223-7/+5
* X86: Fix a typo in call_insn_operandhjl2016-04-211-1/+1
* AVX-512. PR target/70728. Use separate constraint for AVX-512BWkyukhin2016-04-211-7/+8
* * config/i386/i386.md (*lea<mode>_general_1): Rename fromuros2016-04-201-109/+84
* Simplify ix86_expand_vector_move_misalignhjl2016-04-201-171/+81
* [AArch64] Work around PR target/64971ktkachov2016-04-201-0/+15
* gcc/ienkovich2016-04-201-3/+3
* PR70674: S/390: Add memory barrier to stack pointer restore from fpr.krebbel2016-04-202-38/+63
* Remove ssememalignhjl2016-04-193-49/+0
* Remove UNSPEC_LOADU and UNSPEC_STOREUhjl2016-04-197-697/+219
* * config/i386/i386.c (ix86_decompose_address): Use lowpart_subreguros2016-04-192-48/+41
* * tree.h (TYPE_ALIGN, DECL_ALIGN): Return shifted amount.matz2016-04-185-7/+7
* Optimize load double into xmm with zero_extendhjl2016-04-181-6/+6
* * config/i386/mmx.md (*vec_extractv2sf_0): Use gen_lowpart.uros2016-04-182-125/+47
* PR target/70711mwahab2016-04-181-0/+6
* AVX-512. Fix mode size check.kyukhin2016-04-151-1/+1
* config/nvptx/nvptx.opt (moptimize): Add a period at end of help text.amonakov2016-04-151-1/+1
* i386: Don't convert stack operations to pushes if using a redzone.bernds2016-04-153-5/+11
* AVX-512. Fix mem operand modifier for Intel syntax.kyukhin2016-04-151-2/+5
* [gcc]meissner2016-04-141-5/+25
* gcc/ienkovich2016-04-132-7/+7
* 2016-04-12 Eric Botcazou <ebotcazou@adacore.com>ebotcazou2016-04-121-6/+11
* * config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen):jakub2016-04-121-16/+23
* [gcc]meissner2016-04-121-4/+4
* [gcc]meissner2016-04-111-2/+2
* [Patch AArch64 3/3] Fix up for pr70133jgreenhalgh2016-04-111-77/+110
* [Patch AArch64 2/3] Rework the code to print extension strings (pr70133)jgreenhalgh2016-04-114-98/+55
* [Patch AArch64 1/3] Enable CRC by default for armv8.1-ajgreenhalgh2016-04-111-1/+1
* Complete changes to "Ignore -ftree-parallelize-loops={0,1} using gt"tschwinge2016-04-086-11/+12
* [ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsl...ktkachov2016-04-081-2/+4
* * cgraph.h (struct cgraph_simd_clone): Add mask_mode field.jakub2016-04-071-1/+6
* * config/i386/sse.md (shuffletype): Add V32HI and V4TI modes.uros2016-04-061-3/+5
* * config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen):jakub2016-04-061-6/+35
* * config/pa/predicates.md (integer_store_memory_operand): Acceptdanglin2016-04-051-0/+6
* PR target/70510uros2016-04-051-1/+2
* PR target/70525jakub2016-04-051-43/+29
* gcc/olegendo2016-04-031-3/+12
* [AArch64] Fix SIMD predicateevandro2016-04-011-1/+1
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