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* Update copyright years.jakub2015-01-051273-1292/+1287
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219188 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/pa/pa.md (decrement_and_branch_until_zero): Use `Q' constraintdanglin2015-01-032-10/+19
| | | | | | | | | | | | instead of `m' constraint. Likewise for unnamed movb comparison patterns using reg_before_reload_operand predicate. * config/pa/predicates.md (reg_before_reload_operand): Tighten predicate to reject register index and LO_SUM DLT memory forms after reload. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219162 138bc75d-0d04-0410-961f-82ee72b054a4
* Roll ChangeLog file. Limit offsets to 16 bits for moxie.green2015-01-011-1/+2
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219136 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix zero extension for moxiegreen2014-12-301-16/+4
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219116 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/i386.c (ix86_legitimize_address): Declareuros2014-12-301-26/+23
| | | | | | | | | | | | | "changed" as bool. (ix86_expand_unary_operator): Declare "matching_memory" as bool. (ix86_avoid_jump_mispredicts): Declare "isjump" as bool. * config/i386/i386.c (ix86_reassociation_width): Remove unneeded variable "res". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219115 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/i386.c (ix86_legitimize_address): Use std::swap.uros2014-12-301-21/+8
| | | | | | | | | | (ix86_split_fp_branch): Ditto. (ix86_expand_int_movcc): Ditto. (ix86_expand_sse_compare): Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219109 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-12-29 Steve Ellcey <sellcey@mips.com>sje2014-12-292-2/+8
| | | | | | | | | * config/mips/t-mti-linux (MULTILIB_EXCEPTIONS): Add exceptions for mips32[r1] and mips64[r1] with -mnan=2008. * config/mips/t-mti-elf (MULTILIB_EXCEPTIONS): Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219101 138bc75d-0d04-0410-961f-82ee72b054a4
* Issue an error for ms_abi attribute with x32hjl2014-12-271-1/+12
| | | | | | | | | | | | | | | | | | | There is no counter part of x32 in MS ABI. Issue an error when ms_abi attribute is used with x32. gcc/ PR target/64409 * config/i386/i386.c (ix86_function_type_abi): Issue an error when ms_abi attribute is used with x32. gcc/testsuite/ PR target/64409 * gcc.target/i386/pr64409.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219081 138bc75d-0d04-0410-961f-82ee72b054a4
* Switch to 16-bit offsets for moxie ldo/sto instructionsgreen2014-12-276-9/+28
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219080 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/mmx.md (*vec_extractv2sf_1): Do not emit unpckhps.uros2014-12-271-17/+19
| | | | | | | | | | Emit movshdup for SSE3 and shufps otherwise. (*vec_extractv2si_1): Do not emit punpckhdq and unpckhps. Emit pshufd for SSE2 and shufps otherwise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219074 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/olegendo2014-12-241-14/+14
| | | | | | | | PR target/51244 * config/sh/sh.md (*mov_t_msb_neg): Convert split into insn_and_split. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219062 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/64160nickc2014-12-241-6/+8
| | | | | | | | * config/msp430/msp430.md (addsi splitter): Do not split when the destination partially overlaps the source. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219058 138bc75d-0d04-0410-961f-82ee72b054a4
* Add mul.x support for moxiegreen2014-12-244-9/+47
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219056 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/olegendo2014-12-211-3/+9
| | | | | | | | | PR target/55212 * config/sh/sh.md (*addsi3_compact): Add parentheses around && condition. Add comments. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218999 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/64358segher2014-12-202-6/+10
| | | | | | | | | | | | * config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the input operands if only the second is inverted. * config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128): Swap BOOL_REGS_OP1 and BOOL_REGS_OP2. Correct arguments to rs6000_split_logical. (*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2]. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218989 138bc75d-0d04-0410-961f-82ee72b054a4
* MIPSR6: mips-img-elf mips-img-linux-gnu triplets and vendor updatesmpf2014-12-193-1/+76
| | | | | | | | | | | | | | | gcc/ * config.gcc: Support mips*-img-linux* and mips*-img-elf*. * config/mips/mti-linux.h: Support mips32r6 as being the default arch. * config/mips/t-img-elf: New. * config/mips/t-img-linux: New. gcc/testsuite/ * gcc.target/mips/pr37362.c: Skip for mips-img-elf. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218975 138bc75d-0d04-0410-961f-82ee72b054a4
* MIPS32R6 and MIPS64R6 supportmpf2014-12-1912-367/+801
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config.gcc: Add mipsisa64r6 and mipsisa32r6 cpu support. * config/mips/constraints.md (ZD): Add r6 restrictions. * config/mips/gnu-user.h (DRIVER_SELF_SPECS): Add MIPS_ISA_LEVEL_SPEC. * config/mips/loongson.md (<u>div<mode>3, <u>mod<mode>3): Move to mips.md. * config/mips/mips-cpus.def (mips32r6, mips64r6): Define. * config/mips/mips-modes.def (CCF): New mode. * config/mips/mips-protos.h (mips_9bit_offset_address_p): New prototype. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (MIPS_JR): Use JALR $, <reg> for R6. (mips_rtx_cost_data): Add pseudo-processors W32 and W64. (mips_9bit_offset_address_p): New function. (mips_rtx_costs): Account for R6 multiply and FMA instructions. (mips_emit_compare): Implement R6 FPU comparisons. (mips_expand_conditional_move): Implement R6 selects. (mips_expand_conditional_trap): Account for removed trap immediate. (mips_expand_block_move): Disable inline move when LWL/LWR are removed. (mips_print_float_branch_condition): Update for R6 FPU branches. (mips_print_operand): Handle CCF mode compares. (mips_interrupt_extra_call_saved_reg_p): Do not attempt to callee-save MD_REGS for R6. (mips_hard_regno_mode_ok_p): Support CCF mode. (mips_mode_ok_for_mov_fmt_p): Likewise. (mips_secondary_reload_class): CCFmode can be loaded directly. (mips_set_fast_mult_zero_zero_p): Account for R6 multiply instructions. (mips_option_override): Ensure R6 is used with fp64. Set default mips_nan modes. Check for mips_nan support. Prevent DSP with R6. (mips_conditional_register_usage): Disable MD_REGS for R6. Disable FPSW for R6. (mips_mulsidi3_gen_fn): Support R6 multiply instructions. * config/mips/mips.h (ISA_MIPS32R6, ISA_MIPS64R6): Define. (TARGET_CPU_CPP_BUILTINS): Rework for mips32/mips64. (ISA_HAS_JR): New macro. (ISA_HAS_HILO): New macro. (ISA_HAS_R6MUL): Likewise. (ISA_HAS_R6DMUL): Likewise. (ISA_HAS_R6DIV): Likewise. (ISA_HAS_R6DDIV): Likewise. (ISA_HAS_CCF): Likewise. (ISA_HAS_SEL): Likewise. (ISA_HAS_COND_TRAPI): Likewise. (ISA_HAS_FP_MADDF_MSUBF): Likewise. (ISA_HAS_LWL_LWR): Likewise. (ISA_HAS_IEEE_754_LEGACY): Likewise. (ISA_HAS_IEEE_754_2008): Likewise. (ISA_HAS_PREFETCH_9BIT): Likewise. (MIPSR6_9BIT_OFFSET_P): New macro. (BASE_DRIVER_SELF_SPECS): Use MIPS_ISA_DRIVER_SELF_SPECS. (DRIVER_SELF_SPECS): Use MIPS_ISA_LEVEL_SPEC. (MULTILIB_ISA_DEFAULT): Handle mips32r6 and mips64r6. (MIPS_ISA_LEVEL_SPEC): Likewise. (MIPS_ISA_SYNCI_SPEC): Likewise. (ISA_HAS_64BIT_REGS): Likewise. (ISA_HAS_BRANCHLIKELY): Likewise. (ISA_HAS_MUL3): Likewise. (ISA_HAS_DMULT): Likewise. (ISA_HAS_DDIV): Likewise. (ISA_HAS_DIV): Likewise. (ISA_HAS_MULT): Likewise. (ISA_HAS_FP_CONDMOVE): Likewise. (ISA_HAS_8CC): Likewise. (ISA_HAS_FP4): Likewise. (ISA_HAS_PAIRED_SINGLE): Likewise. (ISA_HAS_MADD_MSUB): Likewise. (ISA_HAS_FP_RECIP_RSQRT): Likewise. * config/mips/mips.md (processor): Add w32 and w64. (FPCC): New mode iterator. (reg): Add CCF mode. (fpcmp): New mode attribute. (fcond): Add ordered, ltgt and ne codes. (fcond): Update code attribute. (sel): New code attribute. (selinv): Likewise. (ctrap<mode>4): Update condition. (*conditional_trap_reg<mode>): New define_insn. (*conditional_trap<mode>): Update condition. (mul<mode>3): Expand R6 multiply instructions. (<su>mulsi3_highpart): Likewise. (<su>muldi3_highpart): Likewise. (mul<mode>3_mul3_loongson): Rename... (mul<mode>3_mul3_hilo): To this. Add R6 mul instruction. (<u>mulsidi3_32bit_r6): New expander. (<u>mulsidi3_32bit): Restrict to pre-r6 multiplies. (<u>mulsidi3_32bit_r4000): Likewise. (<u>mulsidi3_64bit): Likewise. (<su>mulsi3_highpart_internal): Likewise. (mulsidi3_64bit_r6dmul): New instruction. (<su>mulsi3_highpart_r6): Likewise. (<su>muldi3_highpart_r6): Likewise. (fma<mode>4): Likewise. (movccf): Likewise. (*sel<code><GPR:mode>_using_<GPR2:mode>): Likewise. (*sel<mode>): Likewise. (<u>div<mode>3): Moved from loongson.md. Add R6 instructions. (<u>mod<mode>3): Likewise. (extvmisalign<mode>): Require ISA_HAS_LWL_LWR. (extzvmisalign<mode>): Likewise. (insvmisalign<mode>): Likewise. (mips_cache): Account for R6 displacement field sizes. (*branch_fp): Rename... (*branch_fp_<mode>): To this. Add CCFmode support. (*branch_fp_inverted): Rename... (*branch_fp_inverted_<mode>): To this. Add CCFmode support. (s<code>_<mode>): Rename... (s<code>_<SCALARF:mode>_using_<FPCC:mode>): To this. Add FCCmode condition support. (s<code>_<mode> swapped): Rename... (s<code>_<SCALARF:mode>_using_<FPCC:mode> swapped): To this. Add CCFmode condition support. (mov<mode>cc GPR): Expand R6 selects. (mov<mode>cc FPR): Expand R6 selects. (*tls_get_tp_<mode>_split): Do not .set push for >= mips32r2. * config/mips/netbsd.h (TARGET_CPU_CPP_BUILTINS): Update similarly to mips.h. (ASM_SPEC): Add mips32r6, mips64r6. * config/mips/t-isa3264 (MULTILIB_OPTIONS, MULTILIB_DIRNAMES): Update for mips32r6/mips64r6. * doc/invoke.texi: Document -mips32r6,-mips64r6. * doc/md.texi: Update comment for ZD constraint. libgcc/ * config.host: Support mipsisa32r6 and mipsisa64r6. * config/mips/mips16.S: Do not build for R6. gcc/testsuite/ * gcc.dg/torture/mips-hilo-2.c: Unconditionally pass for R6 onwards. * gcc.dg/torture/pr19683-1.c: Likewise. * gcc.target/mips/branch-cost-2.c: Require MOVN. * gcc.target/mips/movcc-1.c: Likewise. * gcc.target/mips/movcc-2.c: Likewise. * gcc.target/mips/movcc-3.c: Likewise. * gcc.target/mips/call-saved-4.c: Require LDC. * gcc.target/mips/dmult-1.c: Require R5 or earlier. * gcc.target/mips/fpcmp-1.c: Likewise. * gcc.target/mips/fpcmp-2.c: Likewise. * gcc.target/mips/neg-abs-2.c: Likewise. * gcc.target/mips/timode-1.c: Likewise. * gcc.target/mips/unaligned-1.c: Likewise. * gcc.target/mips/madd-3.c: Require MADD. * gcc.target/mips/madd-9.c: Likewise. * gcc.target/mips/maddu-3.c: Likewise. * gcc.target/mips/msub-3.c: Likewise. * gcc.target/mips/msubu-3.c: Likewise. * gcc.target/mips/mult-1.c: Require INS and not DMUL. * gcc.target/mips/mips-ps-type-2.c: Require MADD.PS. * gcc.target/mips/mips.exp (mips_option_groups): Add ins, dmul, ldc, movn, madd, maddps. (mips-dg-options): INS available from R2. LDC available from MIPS II, DMUL is present in octeon. Describe all features removed from R6. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218973 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EONalalaw012014-12-192-7/+32
| | | | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3): Reparameterize to... (<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant. (xor_one_cmpl<mode>3): New define_insn_and_split. * config/aarch64/iterators.md (NLOGICAL): New define_code_iterator. gcc/testsuite/: * gcc.target/aarch64/eon_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218961 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/notalalaw012014-12-192-10/+18
| | | | | | | | | * config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2): Add SIMD-register variant. * config/aarch64/iterators.md (Vbtype): Add value for SI. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218960 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 1/3] Don't disparage add/sub in SIMD registersalalaw012014-12-191-6/+6
| | | | | | | | | * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize SIMD reg variant. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218958 138bc75d-0d04-0410-961f-82ee72b054a4
* [PATCH][ARM] Fix reservation pattern in cortex-a9-neon.mdjgreenhalgh2014-12-191-1/+1
| | | | | | | | | | | gcc/ * config/arm/cortex-a9-neon.md (cortex_a9_neon_vmov): Change reservation to cortex_a9_neon_dp. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218895 138bc75d-0d04-0410-961f-82ee72b054a4
* * [SH] Split QI/HImode load/store via r0 when LRA is enabled.kkojima2014-12-191-0/+32
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218892 138bc75d-0d04-0410-961f-82ee72b054a4
* * [SH] Add splitter to addsi3_compact.kkojima2014-12-192-7/+35
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218891 138bc75d-0d04-0410-961f-82ee72b054a4
* * [SH] Modify movsi_ie and movsf_ie patterns for LRA.kkojima2014-12-193-2/+138
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218890 138bc75d-0d04-0410-961f-82ee72b054a4
* * [SH] Miscellaneous changes for LRA.kkojima2014-12-195-3/+79
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218889 138bc75d-0d04-0410-961f-82ee72b054a4
* * [SH] Add -mlra option.kkojima2014-12-192-0/+17
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218888 138bc75d-0d04-0410-961f-82ee72b054a4
* * Add TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT target macro.kkojima2014-12-191-0/+28
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218887 138bc75d-0d04-0410-961f-82ee72b054a4
* * Add TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV target macro.kkojima2014-12-191-0/+22
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218886 138bc75d-0d04-0410-961f-82ee72b054a4
* X86-64: Add -mskip-rax-setuphjl2014-12-182-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel never passes floating point arguments around, vararg functions or not. Hence no vector registers are ever used when calling a vararg function. But gcc still dutifully emits an "xor %eax,%eax" before each and every call of a vararg function. Since no callee use that for anything, these instructions are redundant. This patch adds the -mskip-rax-setup option to skip setting up RAX register when SSE is disabled and there are no variable arguments passed in vector registers. Since RAX register is used to avoid unnecessarily saving vector registers on stack when passing variable arguments, the impacts of this option are callees may waste some stack space, misbehave or jump to a random location. GCC 4.4 or newer don't those issues, regardless the RAX register value since they don't check the RAX register value when SSE is disabled. gcc/ * config/i386/i386.c (ix86_expand_call): Skip setting up RAX register for -mskip-rax-setup when there are no parameters passed in vector registers. * config/i386/i386.opt (mskip-rax-setup): New option. * doc/invoke.texi: Document -mskip-rax-setup. gcc/testsuite/ * gcc.target/i386/amd64-abi-7.c: New tests. * gcc.target/i386/amd64-abi-8.c: Likwise. * gcc.target/i386/amd64-abi-9.c: Likwise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218870 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsicalalaw012014-12-182-13/+1
| | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): Handle shift by 64 by moving const0_rtx. (aarch64_ushr_simddi): Delete. * config/aarch64/aarch64.md (enum unspec): Delete UNSPEC_USHR64. gcc/testsuite/: * gcc.target/aarch64/ushr64_1.c: Remove scan-assembler "ushr...64". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218868 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Simplify patterns for sshr_n_[us]64 intrinsicalalaw012014-12-182-15/+5
| | | | | | | | | | | * config/aarch64/aarch64.md (enum "unspec"): Remove UNSPEC_SSHR64. * config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): Change shift amount to 63 if was 64. (aarch64_sshr_simddi): Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218867 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Add TARGET_MIN_DIVISIONS_FOR_RECIP_MULjiwang2014-12-181-0/+9
| | | | | | | | | | | | 2014-12-18 Wilco Dijkstra <wilco.dijkstra@arm.com> * gcc/config/aarch64/aarch64.c (TARGET_MIN_DIVISIONS_FOR_RECIP_MUL): Define. (aarch64_min_divisions_for_recip_mul): New function. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218866 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Generalize code alignmentjiwang2014-12-182-8/+18
| | | | | | | | | | | | | | | | | 2014-12-18 Wilco Dijkstra <wilco.dijkstra@arm.com> * config/aarch64/aarch64-protos.h (tune-params): Add code alignment tuning parameters. * gcc/config/aarch64/aarch64.c (generic_tunings): Add code alignment tuning parameters. (cortexa53_tunings): Likewise. (cortexa57_tunings): Likewise. (thunderx_tunings): Likewise. (aarch64_override_options): Use new alignment tunings. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218865 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/olegendo2014-12-172-49/+54
| | | | | | | | | | | | | | | | | | PR target/51244 * config/sh/sh_treg_combine.cc (is_conditional_insn): New function. (cbranch_trace): Add member rtx* condition_rtx_in_insn, initialize it accordingly in constructor. (cbranch_trace::branch_condition_rtx_ref): New function. (cbranch_trace::branch_condition_rtx): Use branch_condition_rtx_ref. (sh_treg_combine::try_invert_branch_condition): Invert condition rtx in insn using reversed_comparison_code and validate_change instead of invert_jump_1. (sh_treg_combine::execute): Look for conditional insns in basic blocks in addition to conditional branches. * config/sh/sh.md (*movsicc_div0s): Remove combine patterns. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218850 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/olegendo2014-12-171-1/+22
| | | | | | | | | PR target/51244 * config/sh/sh_treg_combine.cc (sh_treg_combine::try_optimize_cbranch): Combine ccreg inversion and cbranch into inverted cbranch. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218847 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Remove "generic_sched" attributejgreenhalgh2014-12-171-8/+0
| | | | | | | | | | gcc/ * config/aarch64/aarch64.md (generic_sched): Delete it. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218829 138bc75d-0d04-0410-961f-82ee72b054a4
* MSP430: Fix unused arg warningjbglaw2014-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The build robot found this: g++ -c -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -Woverloaded-virtual -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Werror -fno-common -DHAVE_CONFIG_H -I. -I. -I../../../gcc/gcc -I../../../gcc/gcc/. -I../../../gcc/gcc/../include -I../../../gcc/gcc/../libcpp/include -I/opt/cfarm/mpc/include -I../../../gcc/gcc/../libdecnumber -I../../../gcc/gcc/../libdecnumber/dpd -I../libdecnumber -I../../../gcc/gcc/../libbacktrace -o msp430.o -MT msp430.o -MMD -MP -MF ./.deps/msp430.TPo ../../../gcc/gcc/config/msp430/msp430.c ../../../gcc/gcc/config/msp430/msp430.c:979:43: error: unused parameter ‘file’ [-Werror=unused-parameter] msp430_asm_output_addr_const_extra (FILE *file, rtx x) ^ cc1plus: all warnings being treated as errors make[2]: *** [msp430.o] Error 1 (See for example this build: http://toolchain.lug-owl.de/buildbot/show_build_details.php?id=384666) Ok for this one? 2014-12-17 Jan-Benedict Glaw <jbglaw@lug-owl.de> * config/msp430/msp430.c (msp430_asm_output_addr_const_extra): Fix unused argument warning. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218828 138bc75d-0d04-0410-961f-82ee72b054a4
* Add -malign-data={abi|compat|cachineline}hjl2014-12-173-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add -malign-data={abi|compat,cachineline} to control how GCC aligns variables. "compat" uses increased alignment value compatible with GCC 4.8 and earlier, "abi" uses alignment value as specified by the psABI, and "cacheline" uses increased alignment value to match the cache line size. "compat" is the default. gcc/ PR target/61296 * config/i386/i386-opts.h (ix86_align_data): New enum. * config/i386/i386.c (ix86_data_alignment): Return the ABI alignment value for -malign-data=abi, the cachine line size for -malign-data=cachineline and the older GCC compatible alignment value for for -malign-data=compat. * config/i386/i386.opt (malign-data=): New. * doc/invoke.texi: Document -malign-data=. gcc/testsuite/ PR target/61296 * gcc.target/i386/pr61296-2.c: New. * gcc.target/i386/pr61296-2.c: Likewise. * gcc.target/i386/pr61296-3.c: Likewise. * gcc.target/i386/pr61296-4.c: Likewise. * gcc.target/i386/pr61296-5.c: Likewise. * gcc.target/i386/pr61296-6.c: Likewise. * gcc.target/i386/pr61296-7.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218818 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/kyukhin2014-12-161-4/+6
| | | | | | | | * config/i386/i386.c (ix86_address_cost): Add explicit restriction to RTL level for the check for PIC register. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218777 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/gnu-user.h (TARGET_CAN_SPLIT_STACK): Move from here ...uros2014-12-163-10/+6
| | | | | | | | | * config/i386/gnu-user64.h (TARGET_CAN_SPLIT_STACK): ... and here ... * config/i386/gnu-user-common.h (TARGET_CAN_SPLIT_STACK): ... to here. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218775 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/64217jasonwucj2014-12-161-1/+1
| | | | | | | | * config/nds32/nds32.md (casesi_internal): Add '=r' for clobber register constraint. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218774 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/rl78/rl78.h: Remove SHORT_IMMEDIATES_SIGN_EXTEND.dj2014-12-151-1/+0
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218768 138bc75d-0d04-0410-961f-82ee72b054a4
* * gcc/config/rs6000/rs6000.md (*add>mode>3_imm_dot,segher2014-12-151-2/+2
| | | | | | | | *add<mode>3_imm_dot2): Change the constraint for the second alternative for operand 1 from "r" to "b". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218750 138bc75d-0d04-0410-961f-82ee72b054a4
* [AARCH64]Fix CLZ_DEFINED_AT_ZERO and CTZ_DEFINED_AT_ZERO definition.renlin2014-12-151-2/+2
| | | | | | | | | | | | | | gcc/ 2014-12-15 Renlin Li <renlin.li@arm.com> * config/aarch64/aarch64.h (CLZ_DEFINED_VALUE_AT_ZERO): Return 2. (CTZ_DEFINED_VALUE_AT_ZERO): Update to support more modes. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218737 138bc75d-0d04-0410-961f-82ee72b054a4
* nvptx: Define valid ASM_OUTPUT_ALIGN.tschwinge2014-12-121-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/nvptx/nvptx.h (ASM_OUTPUT_ALIGN): Define as a C statment. gcc/doc/tm.texi:@defmac ASM_OUTPUT_ALIGN (@var{stream}, @var{power}) gcc/doc/tm.texi-A C statement to output to the stdio stream @var{stream} an assembler gcc/doc/tm.texi-command to advance the location counter to a multiple of 2 to the gcc/doc/tm.texi-@var{power} bytes. @var{power} will be a C expression of type @code{int}. gcc/doc/tm.texi-@end defmac gcc/config/nvptx/nvptx.h:#define ASM_OUTPUT_ALIGN(FILE, POWER) "Empty" is not a C statement, and so in code such as: gcc/dwarf2out.c- if (lsda_encoding == DW_EH_PE_aligned) gcc/dwarf2out.c: ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (PTR_SIZE)); gcc/dwarf2out.c- dw2_asm_output_data (size_of_encoded_value (lsda_encoding), 0, gcc/dwarf2out.c- "Language Specific Data Area (none)"); gcc/varasm.c- if (align > BITS_PER_UNIT) gcc/varasm.c: ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); gcc/varasm.c- assemble_variable_contents (decl, name, dont_output_data); gcc/varasm.c- if (align > 0) gcc/varasm.c: ASM_OUTPUT_ALIGN (asm_out_file, align); gcc/varasm.c- gcc/varasm.c- targetm.asm_out.internal_label (asm_out_file, "LTRAMP", 0); gcc/varasm.c- if (align > BITS_PER_UNIT) gcc/varasm.c: ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); gcc/varasm.c- assemble_constant_contents (exp, XSTR (symbol, 0), align); ..., GCC warns: [...]/source-gcc/gcc/dwarf2out.c: In function 'void output_fde(dw_fde_ref, bool, bool, char*, int, char*, bool, int)': [...]/source-gcc/gcc/dwarf2out.c:665:3: warning: suggest braces around empty body in an 'if' statement [-Wempty-body] ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (PTR_SIZE)); ^ [...]/source-gcc/gcc/varasm.c: In function 'void assemble_variable(tree, int, int, int)': [...]/source-gcc/gcc/varasm.c:2217:2: warning: suggest braces around empty body in an 'if' statement [-Wempty-body] ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); ^ [...]/source-gcc/gcc/varasm.c: In function 'rtx_def* assemble_trampoline_template()': [...]/source-gcc/gcc/varasm.c:2603:5: warning: suggest braces around empty body in an 'if' statement [-Wempty-body] ASM_OUTPUT_ALIGN (asm_out_file, align); ^ [...]/source-gcc/gcc/varasm.c: In function 'void output_constant_def_contents(rtx)': [...]/source-gcc/gcc/varasm.c:3413:2: warning: suggest braces around empty body in an 'if' statement [-Wempty-body] ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); ^ Also, "use" the values, to get rid of that one: [...]/source-gcc/gcc/final.c: In function 'rtx_insn* final_scan_insn(rtx_insn*, FILE*, int, int, int*)': [...]/source-gcc/gcc/final.c:2450:12: warning: variable 'log_align' set but not used [-Wunused-but-set-variable] int log_align; ^ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218689 138bc75d-0d04-0410-961f-82ee72b054a4
* Add use of zex instruction for moxie portgreen2014-12-121-6/+6
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218666 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-12-11 Andrew Pinski <apinski@cavium.com>pinskia2014-12-112-0/+17
| | | | | | | | | | | | | | * config/aarch64/aarch64-protos.h (tune_params): Add align field. * config/aarch64/aarch64.c (generic_tunings): Specify align. (cortexa53_tunings): Likewise. (cortexa57_tunings): Likewise. (thunderx_tunings): Likewise. (aarch64_override_options): Set align_loops, align_jumps, align_functions based on what the tuning struct. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218645 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64]Use AARCH64_FL_FPSIMD flags for all cores in aarch64-cores.defrenlin2014-12-112-8/+6
| | | | | | | | | | | | | | | gcc/ 2014-12-11 Renlin Li <renlin.li@arm.com> * config/aarch64/aarch64-cores.def: Change all AARCH64_FL_FPSIMD to AARCH64_FL_FOR_ARCH8. * config/aarch64/aarch64.c (all_cores): Use FLAGS from aarch64-cores.def file only. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218635 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Fix usage of +no in error message for aarch64_parse_extensionktkachov2014-12-111-1/+2
| | | | | | | | * config/aarch64/aarch64.c (aarch64_parse_extension): Update error message to say +no only when removing extension. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218626 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-12-11 Andrew MacLeod <amacleod@redhat.com>amacleod2014-12-113-0/+10
| | | | | | | | | | | * config/tilepro/gen-mul-tables.cc: Add insn-codes.h to include list for generator file. Add comment indicating it is a generated file. * config/tilepro/mul-tables.c: Update generated file. * config/tilegx/mul-tables.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218624 138bc75d-0d04-0410-961f-82ee72b054a4
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