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* Update copyright years.jakub2015-01-051273-1292/+1287
* * config/pa/pa.md (decrement_and_branch_until_zero): Use `Q' constraintdanglin2015-01-032-10/+19
* Roll ChangeLog file. Limit offsets to 16 bits for moxie.green2015-01-011-1/+2
* Fix zero extension for moxiegreen2014-12-301-16/+4
* * config/i386/i386.c (ix86_legitimize_address): Declareuros2014-12-301-26/+23
* * config/i386/i386.c (ix86_legitimize_address): Use std::swap.uros2014-12-301-21/+8
* 2014-12-29 Steve Ellcey <sellcey@mips.com>sje2014-12-292-2/+8
* Issue an error for ms_abi attribute with x32hjl2014-12-271-1/+12
* Switch to 16-bit offsets for moxie ldo/sto instructionsgreen2014-12-276-9/+28
* * config/i386/mmx.md (*vec_extractv2sf_1): Do not emit unpckhps.uros2014-12-271-17/+19
* gcc/olegendo2014-12-241-14/+14
* PR target/64160nickc2014-12-241-6/+8
* Add mul.x support for moxiegreen2014-12-244-9/+47
* gcc/olegendo2014-12-211-3/+9
* PR target/64358segher2014-12-202-6/+10
* MIPSR6: mips-img-elf mips-img-linux-gnu triplets and vendor updatesmpf2014-12-193-1/+76
* MIPS32R6 and MIPS64R6 supportmpf2014-12-1912-367/+801
* [AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EONalalaw012014-12-192-7/+32
* [AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/notalalaw012014-12-192-10/+18
* [AArch64 1/3] Don't disparage add/sub in SIMD registersalalaw012014-12-191-6/+6
* [PATCH][ARM] Fix reservation pattern in cortex-a9-neon.mdjgreenhalgh2014-12-191-1/+1
* * [SH] Split QI/HImode load/store via r0 when LRA is enabled.kkojima2014-12-191-0/+32
* * [SH] Add splitter to addsi3_compact.kkojima2014-12-192-7/+35
* * [SH] Modify movsi_ie and movsf_ie patterns for LRA.kkojima2014-12-193-2/+138
* * [SH] Miscellaneous changes for LRA.kkojima2014-12-195-3/+79
* * [SH] Add -mlra option.kkojima2014-12-192-0/+17
* * Add TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT target macro.kkojima2014-12-191-0/+28
* * Add TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV target macro.kkojima2014-12-191-0/+22
* X86-64: Add -mskip-rax-setuphjl2014-12-182-1/+10
* [AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsicalalaw012014-12-182-13/+1
* [AArch64] Simplify patterns for sshr_n_[us]64 intrinsicalalaw012014-12-182-15/+5
* [AArch64] Add TARGET_MIN_DIVISIONS_FOR_RECIP_MULjiwang2014-12-181-0/+9
* [AArch64] Generalize code alignmentjiwang2014-12-182-8/+18
* gcc/olegendo2014-12-172-49/+54
* gcc/olegendo2014-12-171-1/+22
* [AArch64] Remove "generic_sched" attributejgreenhalgh2014-12-171-8/+0
* MSP430: Fix unused arg warningjbglaw2014-12-171-1/+1
* Add -malign-data={abi|compat|cachineline}hjl2014-12-173-2/+31
* gcc/kyukhin2014-12-161-4/+6
* * config/i386/gnu-user.h (TARGET_CAN_SPLIT_STACK): Move from here ...uros2014-12-163-10/+6
* PR target/64217jasonwucj2014-12-161-1/+1
* * config/rl78/rl78.h: Remove SHORT_IMMEDIATES_SIGN_EXTEND.dj2014-12-151-1/+0
* * gcc/config/rs6000/rs6000.md (*add>mode>3_imm_dot,segher2014-12-151-2/+2
* [AARCH64]Fix CLZ_DEFINED_AT_ZERO and CTZ_DEFINED_AT_ZERO definition.renlin2014-12-151-2/+2
* nvptx: Define valid ASM_OUTPUT_ALIGN.tschwinge2014-12-121-1/+9
* Add use of zex instruction for moxie portgreen2014-12-121-6/+6
* 2014-12-11 Andrew Pinski <apinski@cavium.com>pinskia2014-12-112-0/+17
* [AArch64]Use AARCH64_FL_FPSIMD flags for all cores in aarch64-cores.defrenlin2014-12-112-8/+6
* [AArch64] Fix usage of +no in error message for aarch64_parse_extensionktkachov2014-12-111-1/+2
* 2014-12-11 Andrew MacLeod <amacleod@redhat.com>amacleod2014-12-113-0/+10
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