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* * config/i386/i386.c (bdesc_args) [IX86_BUILTIN_CVTTPD2DQ256]: Useuros2011-11-021-1/+1
* Move shlib support to toplevel libgccro2011-11-0262-3845/+8
* * config/rs6000/rs6000.c (rs6000_code_end): Declare ATTRIBUTE_UNUSED.amodra2011-11-021-0/+1
* Handle V4HI vector initialization more efficiently on VIS1.davem2011-11-011-0/+24
* * config/i386/i386.md (splitters for int-float conversion): Useuros2011-11-011-9/+27
* 2011-11-01 Andrew Stubbs <ams@codesourcery.com>ams2011-11-011-0/+1
* * config/i386/i386.md (splitters for int-float conversion): Useuros2011-11-011-27/+9
* * config/i386/i386-protos.h (ix86_expand_adjust_ufix_to_sfix_si): Newjakub2011-11-013-24/+62
* * config/i386/i386.md (floatsi<mode>2_vector_sse_with_temp splitter):uros2011-11-011-1/+1
* * config.gcc (powerpc*-*-linux*): Add powerpc*-*-linux*ppc476* variant.bergner2011-11-016-17/+258
* PR target/50910gjl2011-11-014-16/+86
* Add vcond/vcondu patterns to sparc backend.davem2011-11-013-0/+68
* * config/i386/sse.md (fixuns_trunc<mode><sseintvecmodelower>2): Newjakub2011-11-011-0/+29
* * config/i386/sse.md (sseintvecmode): Remove duplicate modes.jakub2011-11-011-24/+24
* Allow zero operand in sparc VIS3 cmask patterns.davem2011-10-311-3/+3
* i386: Remove TARGET_VECTORIZE_BUILTIN_CONVERSION.rth2011-10-313-119/+31
* Slight improvements to vec_init code gen on sparc.davem2011-10-311-0/+105
* * config/i386/i386.md (avx2_vec_dup<mode>): Macroize insn fromuros2011-10-301-129/+51
* PR target/50617danglin2011-10-2911-419/+401
* * config/i386/i386.md (xop_sha<mode>3): Rename from xop_ashl<mode>3.uros2011-10-292-20/+20
* * config/i386/i386.md (lshlv16qi3): Remove expander.uros2011-10-291-60/+46
* PR target/50691danglin2011-10-291-0/+15
* PR target/50887gjl2011-10-297-362/+479
* * config/cris/cris.c (reg_ok_for_base_p, reg_ok_for_index_p,aesok2011-10-294-146/+189
* * config/rs6000/rs6000.md (define_attr "type"): Add vecdouble.pthaugen2011-10-283-42/+56
* * config/i386/sse.md (<shift_insn><mode>3): Fix asm template.uros2011-10-281-1/+1
* * config/i386/i386.md (shift_insn): Rename code attribute fromuros2011-10-283-53/+24
* * config/i386/i386.md (shift_insn): Rename code attribute fromuros2011-10-283-60/+58
* PR target/49313gjl2011-10-281-5/+31
* Implement out-of-line FPR and GPR saves for PPC/Darwiniains2011-10-284-33/+195
* * config/i386/sse.md (VI4SD_AVX2): Removed.jakub2011-10-281-243/+91
* Add support for the VIS3 addxc instruction.davem2011-10-282-8/+86
* Fix constraint on 64-bit VIS3 vector moves.davem2011-10-281-2/+2
* * config/i386/sse.md (avx_cvtpd2dq256_2, avx_cvttpd2dq256_2,jakub2011-10-271-0/+74
* * config/i386/i386.c (ix86_print_operand): Handle 'q' and 'x'jakub2011-10-272-12/+17
* PR target/50875uros2011-10-271-6/+5
* * config/c6x/c6x.c (unit_req_imbalance, res_mii): Cast the first argbernds2011-10-271-13/+5
* PR target/37191uros2011-10-271-56/+56
* Fix thinko in previous sparc setcc changes.davem2011-10-271-0/+5
* Improve sparc setcc generation and add testcases.davem2011-10-262-8/+65
* Canonicalize sparc movcc patterns such that operand 0 always appears in opera...davem2011-10-263-151/+127
* gcc:iains2011-10-261-52/+115
* * config/rs6000/rs6000.c (rs6000_make_savres_rtx): Delete unneededamodra2011-10-263-187/+256
* * config/i386/i386.md (UNSPEC_VSIBADDR): New.jakub2011-10-264-35/+115
* 2011-10-26 Andreas Tobler <andreast@fgznet.ch>andreast2011-10-261-0/+1
* Remove *mmx_maskmovq_rex.hjl2011-10-251-14/+2
* * config/ia64/ia64.c (ia64_profile_hook): Fix thinko.ebotcazou2011-10-251-1/+1
* i386: Delete the vec_extract_even/odd patterns.rth2011-10-251-29/+0
* rs6000: Remove some vec_extract_even/odd expanders.rth2011-10-251-132/+2
* spu: Remove vec_extract_even/odd and vec_interleave expanders.rth2011-10-251-433/+0
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