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* [RS6000] PR72802 part 1, fix constraints for lxssp/stxsspamodra2016-08-081-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | We can't use "o" constraint for lsxxp/stxssp since those insns have a DS-form offset field, ie. the bottom two bits of the offset must be 0. So use "wY" instead, but that leads to finding another problem. mem_operand_gpr is only suitable for gpr loads/stores since it does not enforce multiple-of-4 offsets when -m32. So "wY" can't use mem_operand_gpr, and the vsx tests in mem_operand_gpr are bogus. I've deleted offsettable_mem_14bit_operand because it wasn't used anywhere but in the wY constraint. Note also that the new wY constraint doesn't use memory_operand because that is redundant in a constraint, having already been tested in the predicate. PR target/72802 * config/rs6000/rs6000.c (mem_operand_gpr): Remove vsx dform test. (mem_operand_ds_form): New predicate. * config/rs6000/rs6000-protos.h (mem_operand_ds_form): Declare. * config/rs6000/constraints.md (wY): Use mem_operand_df_form. * config/rs6000/predicates.md (offsettable_mem_14bit_operand): Delete. * config/rs6000/rs6000.md (f32_lm2, f32_sm2): Use wY for SF. (extendsfdf2_fpr): Replace o constraint with wY. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@239233 138bc75d-0d04-0410-961f-82ee72b054a4
* 2016-06-30 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2016-06-301-0/+5
| | | | | | | | | | | | | | | | | | | | PR target/71677 * config/rs6000/constraints.md (wY constraint): New constraint to match the requirements for the LXSD and STXSD instructions. * config/rs6000/predicates.md (offsettable_mem_14bit_operand): New predicate to match the requirements for the LXSD and STXSD instructions. * config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case): Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y' to make sure that the bottom 2 bits of offset are 0, the address form is offsettable, and no updating is done in the address mode. (mov<mode>_hardfloat64, FMOVE64 case): Likewise. (movdi_internal32): Likewise (movdi_internal64): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237898 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2016-06-151-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-06-15 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vsx.md (VSINT_84): Add DImode to enable loading DImode constants with XXSPLTIB in vector registers. (vsx_extract_<mode>, V2DImode/V2DFmode): Combine both vsx_extract_<mode>_internal{1,2} into a single insn that handles direct move (both ISA 2.07 and ISA 3.0 versions), and optimizes extraction of the element at the top of the register as a scalar value. (vsx_extract_<mode>_internal1): Likewise. (vsx_extract_<mode>_internal2): Likewise. * config/rs6000/constraints.md (wi constraint): Remove a comment about DImode not being allowed in Altivec registers. (wB constraint): New constraint for constants that can be generated in Altivec registers with VSPLTISW/VUPKHSW. * config/rs6000/predicates.md (xxspltib_constant_split): Update comments. (xxspltib_constant_nosplit): Likewise. * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Add support for -mupper-regs-di to enable DImode to go into Altivec registers. (POWERPC_MASKS): Likewise. (power7 cpu): Likewise. * config/rs6000/rs6000.opt (-mupper-regs-di): Likewise. * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support for DImode being allowed in Altivec registers. Update wi/wj constraints. Set scalar_in_vmx_p flag. (rs6000_option_override_internal): Add checks for -mupper-regs-di. (xxspltib_constant_p): Allow CONST_INT's with VOIDmode. Don't return true if we could use VSPLTISW/VUPKHSW instead of XXSPLTIB. (rs6000_opt_masks): Add -mupper-regs-di. * config/rs6000/rs6000.md (lfiwax): Update clobbers that don't use direct move to use wi and not wj. (lfiwzx): Likewise. (floatsi<mode>2_lfiwax_mem): Combine alternatives into a single alternative. (floatunssi<mode>2_lfiwzx_mem): Likewise. (fix_trunc<mode>di2_fctidz): Change second alternative to allow any VSX register, instead of just Altivec registers, to allow either operand to be an Altivec register or both. (fixuns_trunc<mode>di2_fctiduz): Likewise. (movdi_internal32): Add support for -mupper-regs-di. Add support to load constants via XXSPLTIB or VSPLTISW. Add spacing to allow the alternatives and attributes to be lined up to be easier to read. (movdi_internal64): Likewise. (64-bit DImode splitters): Change predicates to only split loading up GPR registers. Add splits for using XXSPLTIB or VSPLTISW to load constants in ISA 3.0 or ISA 2.07 respectively. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mupper-regs-di. Update -mupper-regs-df and -mupper-regs-sf to mention -mcpu=power9 sets these options. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the wB constraint. [gcc/testsuite] 2016-06-15 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-dimode1.c: New test. * gcc.target/powerpc/p9-dimode2.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237490 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2016-05-181-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/70915 * config/rs6000/constraints.md (wE constraint): New constraint for a vector constant that can be loaded with XXSPLTIB. (wM constraint): New constraint for a vector constant of a 1's. (wS constraint): New constraint for a vector constant that can be loaded with XXSPLTIB and a vector sign extend instruction. * config/rs6000/predicates.md (xxspltib_constant_split): New predicates for wE/wS constraints. (xxspltib_constant_nosplit): Likewise. (easy_vector_constant): Add support for constants that can be loaded via XXSPLTIB. (all_ones_constant): New predicate for vector constant with all 1's set. (splat_input_operand): Add support for ISA 3.0 word splat operations. * config/rs6000/rs6000.c (xxspltib_constant_p): New function to return if a constant can be loaded with the ISA 3.0 XXSPLTIB instruction and possibly with a sign extension. (output_vec_const_move): Add support for XXSPLTIB. If we are loading up 0/-1 into Altivec registers, prefer using VSPLTISW instead of XXLXOR/XXLORC. (rs6000_expand_vector_init): Add support for ISA 3.0 word splat operations. (rs6000_legitimize_reload_address): Likewise. (rs6000_output_move_128bit): Use output_vec_const_move to emit constants. * config/rs6000/vsx.md (VSX_M): Add TImode (if -mvsx-timode) and combine VSX_M and VSX_M2 into one iterator. (VSX_M2): Likewise. (VSINT_84): New iterators for loading constants with XXSPLTIB. (VSINT_842): Likewise. (UNSPEC_VSX_SIGN_EXTEND): New UNSPEC. (xxspltib_v16qi): New insns to load up constants with the ISA 3.0 XXSPLTIB instruction. (xxspltib_<mode>_nosplit): Likewise. (xxspltib_<mode>_split): New insn to load up constants with XXSPLTIB and a sign extend instruction. (vsx_mov<mode>): Replace single move that handled all vector types with separate 32-bit and 64-bit moves. Combine the movti_<bit> moves (when -mvsx-timode is in effect) into the main vector moves. Eliminate separate moves for <VSr> <VSa>, where the preferred register class (<VSr>) is listed first, and the secondary register class (<VSa>) is listed second with a '?' to discourage use. Prefer loading 0/-1 in any VSX register for ISA 3.0, and Altivec registers for ISA 2.06/2.07 (PR target/70915) so that if the register was involved in a slow operation, the clear/set operation does not wait for the slow operation to finish. Adjust the length attributes for 32-bit mode. Use rs6000_output_move_128bit and drop the use of the string instructions for 32-bit movti when -mvsx-timode is in effect. Use spacing so that the alternatives and attributes don't generate long lines, and put things in columns, so that it is easier to match up the operands and attributes with the insn alternatives. (vsx_mov<mode>_64bit): Likewise. (vsx_mov<mode>_32bit): Likewise. (vsx_movti_64bit): Fold movti into normal vector moves. (vsx_movti_32bit): Likewise. (vsx_splat_<mode>, V4SI/V4SF modes): Add support for ISA 3.0 word spat instructions. (vsx_splat_v4si_internal): Likewise. (vsx_splat_v4sf_internal): Likewise. (vector fusion peepholes): Use VSX_M instead of VSX_M2. (vsx_sign_extend_qi_<mode>): New ISA 3.0 instructions to sign extend vector elements. (vsx_sign_extend_hi_<mode>): Likewise. (vsx_sign_extend_si_v2di): Likewise. * config/rs6000/rs6000-protos.h (xxspltib_constant_p): Add declaration. * doc/md.texi (PowerPC constraints): Document the wE, wM, and wS constraints. Add trailing period to wL documentation. [gcc/testsuite] 2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-splat-1.c: New tests for ISA 3.0 word splat operations and the XXSPLTIB instruction. * gcc.target/powerpc/p9-splat-2.c: Likewise. * gcc.target/powerpc/p9-splat-3.c: Likewise. * gcc.target/powerpc/pr47755.c: Allow vspltisw in addition to xxlxor to clear a register. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236394 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2016-05-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/predicates.md (quad_memory_operand): Move most of the code into quad_address_p and call it to share code with vsx_quad_dform_memory_operand. (vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector d-form support. * config/rs6000/rs6000.opt (-mlra): Switch to being an option mask bit instead of being a separate word. Split -mpower9-dform into two switches, -mpower9-dform-scalar and -mpower9-dform-vector. * config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask for the register class supporting 128-bit quad word memory offsets. (mode_supports_vsx_dform_quad): Helper function to return if the register class uses quad word memory offsets. (rs6000_debug_addr_mask): Add support for quad word memory offsets. (rs6000_debug_reg_global): Always print if we are using LRA or not. (rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form instructions are enabled, set up the appropriate addr_masks for 128-bit types. (rs6000_init_hard_regno_mode_ok): wb constraint is now based on -mpower9-dform-scalar, instead of -mpower9-dform. (rs6000_option_override_internal): Split -mpower9-dform into two switches, -mpower9-dform-scalar and -mpower9-dform-vector. The -mpower9-dform switch sets or clears both. If we are not using the LRA register allocator, do not enable -mpower9-dform-vector by default. If we are using LRA, enable -mpower9-dform-vector and -mvsx-timode if it is appropriate. Issue a warning if either -mpower9-dform-vector or -mvsx-timode are explicitly used without enabling LRA. (quad_address_offset_p): New helper function to return if the offset is legal for quad word memory instructions. (quad_address_p): New function to determin if GPR or vector register quad word memory addresses are legal. (mem_operand_gpr): Validate quad word address offsets. (reg_offset_addressing_ok_p): Add support for ISA 3.0 vector d-form (register + offset) instructions. (offsettable_ok_by_alignment): Likewise. (rs6000_legitimate_offset_address_p): Likewise. (legitimate_lo_sum_address_p): Likewise. (rs6000_legitimize_address): Likewise. (rs6000_legitimize_reload_address): Add more debug statements for -mdebug=addr. (rs6000_legitimate_address_p): Add support for ISA 3.0 vector d-form instructions. (rs6000_secondary_reload_memory): Add support for ISA 3.0 vector d-form instructions. Distinguish different cases in debug output. (rs6000_secondary_reload_inner): Add support for ISA 3.0 vector d-form instructions. (rs6000_preferred_reload_class): Likewise. (rs6000_output_move_128bit): Add support for ISA 3.0 d-form instructions. If ISA 3.0 is available, generate lxvx/stxvx instead of the ISA 2.06 indexed memory instructions. (rs6000_emit_prologue): If we have ISA 3.0 d-form instructions, use them to save/restore the saved vector registers instead of using Altivec instructions. (rs6000_emit_epilogue): Likewise. (rs6000_lra_p): Use TARGET_LRA instead of the old option word. (rs6000_opt_masks): Split -mpower9-dform into -mpower9-dform-scalar and -mpower9-dform-vector. (rs6000_print_options_internal): Print -mno-<switch> if <switch> was not selected. * config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit ISA 3.0 vector indexed memory instructions, and fold the code into the normal mov<mode> patterns. (p9_vecstore_<mode>): Likewise. (vsx_mov<mode>): Add support for ISA 3.0 vector d-form instructions. (vsx_movti_64bit): Likewise. (vsx_movti_32bit): Likewise. * config/rs6000/constraints.md (wO constraint): New constraint for ISA 3.0 vector d-form support. * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use -mpower9-dform-scalar instead of -mpower9-dform. Add note not to include -mpower9-dform-vector until we switch over to LRA. (POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two. switches, -mpower9-dform-scalar and -mpower9-dform-vector. * config/rs6000/rs6000-protos.h (quad_address_p): Add declaration. * doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation for -mpower9-dform and -mlra. * doc/md.texi (wO constraint): Document wO constraint. [gcc/testsuite] 2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form support. * gcc.target/powerpc/dform-1.c: Add -mlra option to silence warning when using -mvsx-timode. * gcc.target/powerpc/p8vector-int128-1.c: Likewise. * gcc.target/powerpc/dform-2.c: Likewise. * gcc.target/powerpc/pr68805.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236133 138bc75d-0d04-0410-961f-82ee72b054a4
* [RS6000] PR70052, ICE compiling _Decimal128 test caseamodra2016-03-251-1/+1
| | | | | | | | | | | | | | | | | | gcc/ PR target/70052 * config/rs6000/constraints.md (j): Simplify. * config/rs6000/predicates.md (easy_fp_constant): Exclude decimal float 0.D. * config/rs6000/rs6000.md (zero_fp): New mode_attr. (mov<mode>_hardfloat, mov<mode>_hardfloat32, mov<mode>_hardfloat64, mov<mode>_64bit_dm, mov<mode>_32bit): Use zero_fp in place of j in all constraint alternatives. (movtd_64bit_nodm): Delete "j" constraint alternative. gcc/testsuite/ * gcc.dg/dfp/pr70052.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234479 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2016-01-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (wo constraint): New constraint for ISA 3.0 (power9). * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add support for wo constraint. (rs6000_init_hard_regno_mode_ok): Likewise. * config/rs6000/rs6000.h (r6000_reg_class_enum): Add support for wo constraint. * config/rs6000/altivec.md (altivec_vperm_<mode>): Clean up vperm expanders not to have constraints. Add support for ISA 3.0 xxperm instruction. Add support for fusing xxlor with xxperm. (altivec_vperm_<mode>_internal): Likewise. (altivec_vperm_v8hiv16qi): Likewise. (altivec_vperm_<mode>v16q): Likewise. (altivec_vperm_<mode>_uns): Likewise. (vperm_v8hiv4si): Likewise. (vperm_v16qiv8hi): Likewise. * doc/md.texi (RS/6000 constraints): Document wo constraint. [gcc/testsuite] 2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-permute.c: New test for xxperm code generation. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232060 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years.jakub2016-01-041-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232055 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2015-11-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2015-11-25 Michael Meissner <meissner@linux.vnet.ibm.com> <patch #10> * config/rs6000/constraints.md (wb constraint): New constraint for ISA 3.0 d-form scalar addressing. * config/rs6000/rs6000.c (mode_supports_vmx_dform): Add support for ISA 3.0 D-form addressing to load SFmode/DFmode scalars into Altivec registers. Add wb constraint for Altivec registers with D-form addressing. If we have ISA 3.0 d-form support, undo secondary reload support for using FPR registers if we want to do D-form addressing. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_secondary_reload): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wb constraint. * config/rs6000/rs6000.md (f32_lr2 mode attribute): Add support for ISA 3.0 SFmode/DFmode d-form addressing to Altivec registers. (f32_lm2): Likewise. (f32_li2): Likewise. (f32_sr2): Likewise. (f32_sm2): Likewise. (f32_si2): Likewise. (f64_p9): Likewise. (extendsfdf2_fpr): Likewise. (mov<mode>_hardfloat): Likewise. (mov<mode>_hardfloat32): Likewise. (mov<mode>_hardfloat64): Likewise. * doc/md.texi (RS/6000 constraints): Document wb constraint. Fixup we constraint documentation. [gcc/testsuite] 2015-11-25 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/dform-1.c: New test. * gcc.target/powerpc/dform-2.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230913 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2015-11-131-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (we constraint): New constraint for 64-bit power9 vector support. (wL constraint): New constraint for the element in a vector that can be addressed by the MFVSRLD instruction. * config/rs6000/rs6000-protos.h (convert_float128_to_int): Add declaration. (convert_int_to_float128): Likewise. (rs6000_generate_compare): Add support for ISA 3.0 (power9) hardware support for IEEE 128-bit floating point. (rs6000_expand_float128_convert): Likewise. (convert_float128_to_int): Likewise. (convert_int_to_float128): Likewise. * config/rs6000/rs6000.md (UNSPEC_ROUND_TO_ODD): New unspecs for ISA 3.0 hardware IEEE 128-bit floating point. (UNSPEC_IEEE128_MOVE): Likewise. (UNSPEC_IEEE128_CONVERT): Likewise. (FMA_F): Add support for IEEE 128-bit floating point hardware support. (Ff): Add support for DImode. (Fv): Likewise. (any_fix code iterator): New and updated iterators for IEEE 128-bit floating point hardware support. (any_float code iterator): Likewise. (s code attribute): Likewise. (su code attribute): Likewise. (az code attribute): Likewise. (uns code attribute): Likewise. (neg<mode>2, FLOAT128 iterator): Add support for IEEE 128-bit floating point hardware support. (abs<mode>2, FLOAT128 iterator): Likewise. (add<mode>3, IEEE128 iterator): New insns for IEEE 128-bit floating point hardware. (sub<mode>3, IEEE128 iterator): Likewise. (mul<mode>3, IEEE128 iterator): Likewise. (div<mode>3, IEEE128 iterator): Likewise. (copysign<mode>3, IEEE128 iterator): Likewise. (sqrt<mode>2, IEEE128 iterator): Likewise. (neg<mode>2, IEEE128 iterator): Likewise. (abs<mode>2, IEEE128 iterator): Likewise. (nabs<mode>2, IEEE128 iterator): Likewise. (fma<mode>4_hw, IEEE128 iterator): Likewise. (fms<mode>4_hw, IEEE128 iterator): Likewise. (nfma<mode>4_hw, IEEE128 iterator): Likewise. (nfms<mode>4_hw, IEEE128 iterator): Likewise. (extend<SFDF:mode><IEEE128:mode>2_hw): Likewise. (trunc<mode>df2_hw, IEEE128 iterator): Likewise. (trunc<mode>sf2_hw, IEEE128 iterator): Likewise. (fix_fixuns code attribute): Likewise. (float_floatuns code attribute): Likewise. (fix<uns>_<mode>si2_hw): Likewise. (fix<uns>_<mode>di2_hw): Likewise. (float<uns>_<mode>si2_hw): Likewise. (float<uns>_<mode>di2_hw): Likewise. (xscvqp<su>wz_<mode>): Likewise. (xscvqp<su>dz_<mode>): Likewise. (xscv<su>dqp_<mode): Likewise. (ieee128_mfvsrd): Likewise. (ieee128_mfvsrwz): Likewise. (ieee128_mtvsrw): Likewise. (ieee128_mtvsrd): Likewise. (trunc<mode>df2_odd): Likewise. (cmp<mode>_h): Likewise. (128-bit GPR splitters): Don't split a 128-bit move that is a direct move between GPR and vector registers using ISA 3.0 direct move instructions. (<u>mul<mode><dmode>3): Add support for the ISA 3.0 integer multiply-add instruction. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add ISA 3.0 debugging. (rs6000_init_hard_regno_mode_ok): If ISA 3.0 and 64-bit, enable we constraint. Disable the VSX<->GPR direct move helpers if we have the MFVSRLD and MTVSRDD instructions. (rs6000_secondary_reload_simple_move): Add support for doing vector direct moves directly without additional scratch registers if we have ISA 3.0 instructions. (rs6000_secondary_reload_direct_move): Update comments. (rs6000_output_move_128bit): Add support for ISA 3.0 vector instructions. * config/rs6000/vsx.md (vsx_mov<mode>): Add support for ISA 3.0 direct move instructions. (vsx_movti_64bit): Likewise. (vsx_extract_<mode>): Likewise. * config/rs6000/rs6000.h (VECTOR_ELEMENT_MFVSRLD_64BIT): New macros for ISA 3.0 direct move instructions. (TARGET_DIRECT_MOVE_128): Likewise. (TARGET_MADDLD): Add support for the ISA 3.0 integer multiply-add instruction. * doc/md.texi (RS/6000 constraints): Document we, wF, wG, wL constraints. Update wa documentation to say not to use %x<n> on instructions that only take Altivec registers. [gcc/testsuite] 2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/float128-hw.c: New test for IEEE 128-bit hardware floating point support. * gcc.target/powerpc/direct-move-vector.c: New test for 128-bit vector direct move instructions. * gcc.target/powerpc/maddld.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230342 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2015-11-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2015-11-08 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (wF constraint): New constraints for power9/toc fusion. (wG constraint): Likewise. * config/rs6000/predicates.md (u6bit_cint_operand): New predicate, recognize 0..63. (upper16_cint_operand): New predicate for power9 and toc fusion. (fpr_reg_operand): Likewise. (toc_fusion_or_p9_reg_operand): Likewise. (toc_fusion_mem_raw): Likewise. (toc_fusion_mem_wrapped): Likewise. (fusion_gpr_addis): If power9 fusion, allow fusion for a larger address range. (fusion_gpr_mem_combo): Delete, use fusion_addis_mem_combo_load instead. (fusion_addis_mem_combo_load): Add support for power9 fusion of floating point loads, floating point stores, and gpr stores. (fusion_addis_mem_combo_store): Likewise. (fusion_offsettable_mem_operand): Likewise. * config/rs6000/rs6000-protos.h (emit_fusion_addis): Add declarations. (emit_fusion_load_store): Likewise. (fusion_p9_p): Likewise. (expand_fusion_p9_load): Likewise. (expand_fusion_p9_store): Likewise. (emit_fusion_p9_load): Likewise. (emit_fusion_p9_store): Likewise. (fusion_wrap_memory_address): Likewise. * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add new elements for power9 fusion. (rs6000_debug_print_mode): Rework debug information to print more information about fusion. (rs6000_init_hard_regno_mode_ok): Setup for power9 fusion support. (rs6000_legitimate_address_p): Recognize toc fusion as a valid offsettable memory address. (rs6000_rtx_costs): Update costs for new ISA 3.0 instructions. (emit_fusion_gpr_load): Move most of the code from emit_fusion_gpr_load into emit_fusion-addis that handles both power8 and power9 fusion. (emit_fusion_addis): Likewise. (emit_fusion_load_store): Likewise. (fusion_wrap_memory_address): Add support for TOC fusion. (fusion_split_address): Likewise. (fusion_p9_p): Add support for power9 fusion. (expand_fusion_p9_load): Likewise. (expand_fusion_p9_store): Likewise. (emit_fusion_p9_load): Likewise. (emit_fusion_p9_store): Likewise. * config/rs6000/rs6000.h (TARGET_EXTSWSLI): Macros for support for new instructions in ISA 3.0. (TARGET_CTZ): Likewise. (TARGET_TOC_FUSION_INT): Macros for power9 fusion support. (TARGET_TOC_FUSION_FP): Likewise. * config/rs6000/rs6000.md (UNSPEC_FUSION_P9): New power9/toc fusion unspecs. (UNSPEC_FUSION_ADDIS): Likewise. (QHSI mode iterator): New iterator for power9 fusion. (GPR_FUSION): Likewise. (FPR_FUSION): Likewise. (mod<mode>3): Add support for ISA 3.0 modulus instructions. (umod<mode>3): Likewise. (divmod peephole): Likewise. (udivmod peephole): Likewise. (ctz<mode>2): Add support for ISA 3.0 count trailing zeros scalar instructions. (ctz<mode>2_h): Likewise. (ashdi3_extswsli): Add support for ISA 3.0 EXTSWSLI instruction. (ashdi3_extswsli_dot): Likewise. (ashdi3_extswsli_dot2): Likewise. (power9 fusion splitter): New power9/toc fusion support. (toc_fusionload_<mode>): Likewise. (toc_fusionload_di): Likewise. (fusion_gpr_load_<mode>): Update predicate function. (power9 fusion peephole2s): New power9/toc fusion support. (fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load): Likewise. (fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store): Likewise. (fusion_fpr_<P:mode>_<FPR_FUSION:mode>_load): Likewise. (fusion_fpr_<P:mode>_<FPR_FUSION:mode>_store): Likewise. (fusion_p9_<mode>_constant): Likewise. [gcc/testsuite] 2015-11-08 Michael Meissner <meissner@linux.vnet.ibm.com> * lib/target-supports.exp (check_p8vector_hw_available): Split long line. (check_vsx_hw_available): Likewise. (check_p9vector_hw_available): Add new checks for ISA 3.0 hardware support and for PowerPC float128 support. (check_p9modulo_hw_available): Likewise. (check_ppc_float128_sw_available): Likewise. (check_ppc_float128_hw_available): Likewise. (check_effective_target_powerpc_p9vector_ok): Likewise. (check_effective_target_powerpc_p9modulo_ok): Likewise. (check_effective_target_powerpc_float128_sw_ok): Likewise. (check_effective_target_powerpc_float128_hw_ok): Likewise. (is-effective-target): Add new PowerPc targets. (is-effective-target-keyword): Likewise. (check_vect_support_and_set_flags): If we have ISA 3.0 vector instructions, use it. * gcc.target/powerpc/mod-1.c: New test for ISA 3.0 instructions. * gcc.target/powerpc/mod-2.c: Likewise. * gcc.target/powerpc/ctz-1.c: Likewise. * gcc.target/powerpc/ctz-2.c: Likewise. * gcc.target/powerpc/extswsli-1.c: Likewise. * gcc.target/powerpc/extswsli-2.c: Likewise. * gcc.target/powerpc/extswsli-3.c: Likewise. * gcc.target/powerpc/fusion.c (fusion_vector): Move to fusion2.c and allow the test on PowerPC LE. * gcc.target/powerpc/fusion2.c (fusion_vector): Likewise. * gcc.target/powerpc/fusion3.c: New file, test power9 fusion. * gcc.target/powerpc/float128-call.c: Use powerpc_float128_sw_ok check instead of powerpc_vsx_ok. * gcc.target/powerpc/float128-mix.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230066 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-08-03 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2015-08-031-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/vector.md (VEC_L): Add KFmode and TFmode. (VEC_M): Likewise. (VEC_N): Likewise. (mov<mode>, VEC_M iterator): Add support for IEEE 128-bit floating point in VSX registers. * config/rs6000/constraints.md (wb constraint): Document unused w<x> constraint. (we constraint): Likewise. (wo constraint): Likewise. (wp constraint): New constraint for IEEE 128-bit floating point in VSX registers. (wq constraint): Likewise. * config/rs6000/predicates.md (easy_fp_constant): Add support for IEEE 128-bit floating point in VSX registers. (easy_scalar_constant): Likewise. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add new constraints (wp, wq) for IEEE 128-bit floating point in VSX registers. (rs6000_init_hard_regno_mode_ok): Likewise. * config/rs6000/vsx.md (VSX_LE_128): Add support for IEEE 128-bit floating point in VSX registers. (VSX_L): Likewise. (VSX_M): Likewise. (VSX_M2): Likewise. (VSm): Likewise. (VSs): Likewise. (VSr): Likewise. (VSa): Likewise. (VSv): Likewise. (vsx_le_permute_<mode>): Add support to properly swap bytes for IEEE 128-bit floating point in VSX registers on little endian. (vsx_le_undo_permute_<mode>): Likewise. (vsx_le_perm_load_<mode>): Likewise. (vsx_le_perm_store_<mode>): Likewise. (splitters for IEEE 128-bit fp moves): Likewise. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wp and wq constraints. * config/rs6000/altivec.md (VM): Add support for IEEE 128-bit floating point in VSX registers. (VM2): Likewise. * doc/md.text (Machine Constraints): Document wp and wq constraints on PowerPC. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226520 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/66217segher2015-07-201-19/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/constraints.md ("S", "T", "t"): Delete. Update "available letters" comment. * config/rs6000/predicates.md (mask_operand, mask_operand_wrap, mask64_operand, mask64_2_operand, any_mask_operand, and64_2_operand, and_2rld_operand): Delete. (and_operand): Adjust. (rotate_mask_operator): New. * config/rs6000/rs6000-protos.h (build_mask64_2_operands, includes_lshift_p, includes_rshift_p, includes_rldic_lshift_p, includes_rldicr_lshift_p, insvdi_rshift_rlwimi_p, extract_MB, extract_ME): Delete. (rs6000_is_valid_mask, rs6000_is_valid_and_mask, rs6000_is_valid_shift_mask, rs6000_is_valid_insert_mask, rs6000_insn_for_and_mask, rs6000_insn_for_shift_mask, rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and, rs6000_emit_2insn_and): New. * config/rs6000/rs6000.c (num_insns_constant): Adjust. (build_mask64_2_operands, includes_lshift_p, includes_rshift_p, includes_rldic_lshift_p, includes_rldicr_lshift_p, insvdi_rshift_rlwimi_p, extract_MB, extract_ME): Delete. (rs6000_is_valid_mask, rs6000_is_valid_and_mask, rs6000_insn_for_and_mask, rs6000_is_valid_shift_mask, s6000_insn_for_shift_mask, rs6000_is_valid_insert_mask, rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and, rs6000_emit_2insn_and): New. (print_operand) <'b', 'B', 'm', 'M', 's', 'S', 'W'>: Delete. (rs6000_rtx_costs) <CONST_INT>: Delete mask_operand and mask64_operand handling. <NOT>: Don't fall through to next case. <AND>: Handle the various rotate-and-mask cases directly. <IOR>: Always cost as one insn. * config/rs6000/rs6000.md (splitter for bswap:SI): Adjust. (and<mode>3): Adjust expander for the new patterns. (and<mode>3_imm, and<mode>3_imm_dot, and<mode>3_imm_dot2, and<mode>3_imm_mask_dot, and<mode>3_imm_mask_dot2): Adjust condition. (*and<mode>3_imm_dot_shifted): New. (*and<mode>3_mask): Delete, rewrite as ... (and<mode>3_mask): ... New. (*and<mode>3_mask_dot, *and<mode>3_mask_dot): Rewrite. (andsi3_internal0_nomc): Delete. (*andsi3_internal6): Delete. (*and<mode>3_2insn): New. (insv, insvsi_internal, *insvsi_internal1, *insvsi_internal2, *insvsi_internal3, *insvsi_internal4, *insvsi_internal5, *insvsi_internal6, insvdi_internal, *insvdi_internal2, *insvdi_internal3): Delete. (*rotl<mode>3_mask, *rotl<mode>3_mask_dot, *rotl<mode>3_mask_dot2, *rotl<mode>3_insert, *rotl<mode>3_insert_2, *rotl<mode>3_insert_3, *rotl<mode>3_insert_4, two splitters for multi-precision shifts, *ior<mode>_mask): New. (extzv, extzvdi_internal, *extzvdi_internal1, *extzvdi_internal2, *rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2, *ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2, *lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2): Delete. (ashr<mode>3): Delete expander. (*ashr<mode>3): Rename to ... (ashr<mode>3): ... This. (ashrdi3_no_power, *ashrdisi3_noppc64be): Delete. (*rotldi3_internal4, *rotldi3_internal5 and split, *rotldi3_internal6 and split, *ashldi3_internal4, ashldi3_internal5 and split, *ashldi3_internal6 and split, *ashldi3_internal7, ashldi3_internal8 and split, *ashldi3_internal9 and split): Delete. (*anddi3_2rld, *anddi3_2rld_dot, *anddi3_2rld_dot2): Delete. (splitter for loading a mask): Adjust. * doc/md.texi (Machine Constraints): Remove q, S, T, t constraints. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226005 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/rs6000/constraints.md (Y, U): Use match_test.dje2015-05-261-2/+2
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223702 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years.jakub2015-01-051-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219188 138bc75d-0d04-0410-961f-82ee72b054a4
* PR63426 Fix various signed integer overflowstrippels2014-11-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | Running the testsuite after bootstrap-ubsan on gcc112 shows several issues. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63426 for the full list. This patch fixes several of them. 2014-11-20 Markus Trippelsdorf <markus@trippelsdorf.de> * config/rs6000/constraints.md: Avoid signed integer overflows. * config/rs6000/predicates.md: Likewise. * config/rs6000/rs6000.c (num_insns_constant_wide): Likewise. (includes_rldic_lshift_p): Likewise. (includes_rldicr_lshift_p): Likewise. * emit-rtl.c (const_wide_int_htab_hash): Likewise. * loop-iv.c (determine_max_iter): Likewise. (iv_number_of_iterations): Likewise. * tree-ssa-loop-ivopts.c (get_computation_cost_at): Likewise. * varasm.c (get_section_anchor): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217886 138bc75d-0d04-0410-961f-82ee72b054a4
* rs6000: Fix signed integer overflowstrippels2014-11-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | bootstrap-ubsan on gcc112 shows a couple of signed integer overflows: config/rs6000/constraints.md:143:33: runtime error: signed integer overflow: 9223372036854775807 + 32768 cannot be represented in type 'long int' config/rs6000/predicates.md:396:22: runtime error: signed integer overflow: 9223372036854775807 + 2147516416 cannot be represented in type 'long int' config/rs6000/predicates.md:856:11: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:862:12: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:865:11: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:868:12: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:914:11: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:917:12: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:940:11: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:946:12: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:949:11: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself config/rs6000/predicates.md:955:12: runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself 2014-11-19 Markus Trippelsdorf <markus@trippelsdorf.de> * config/rs6000/constraints.md: Avoid signed integer overflows. * config/rs6000/predicates.md: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217785 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-08-221-1/+1
| | | | | | | | | | | | | | | | | PR target/62195 * doc/md.texi (Machine Constraints): Update PowerPC wi constraint documentation to state it is only for VSX operations. * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi constraint only active if VSX. * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions. (lfiwzx): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214329 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-08-17 Segher Boessenkool <segher@kernel.crashing.org>segher2014-08-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/constraints.md ("S"): Require TARGET_POWERPC64. * config/rs6000/htm.md (ttest): Remove clobber. * config/rs6000/predicates.md (any_mask_operand): New predicate. (and_operand): Reformat. (and_2rld_operand): New predicate. * config/rs6000/rs6000-protos.h (rs6000_split_logical): Remove last parameter. * config/rs6000/rs6000.c (rs6000_split_logical_inner): Remove last parameter. Handle AND directly. (rs6000_split_logical_di): Remove last parameter. (rs6000_split_logical): Remove last parameter. Remove obsolete comment. * config/rs6000/rs6000.md (BOOL_REGS_AND_CR0): Delete. (one_cmpl<mode>2): Adjust call of rs6000_split_logical. (ctz<mode>2, ffs<mode>2): Delete clobber. Reformat. (andsi3, andsi3_mc, andsi3_nomc, *andsi3_internal2_mc, *andsi3_internal3_mc, *andsi3_internal4, *andsi3_internal5_mc, and 5 anonymous splitters): Delete. (and<mode>3): New expander. (*and<mode>3, *and<mode>3_dot, *and<mode>3_dot2): New. (and<mode>3_imm, *and<mode>3_imm_dot, *and<mode>3_imm_dot2): New. (*and<mode>3_mask, *and<mode>3_mask_dot, *and<mode>3_mask_dot2): New. (ior<mode>, xor<mode>3): Adjust call of rs6000_split_logical. (floatdisf2_internal1): Remove clobbers. (anddi3, anddi3_mc, anddi3_nomc, anddi3_internal2_mc, *anddi3_internal3_mc, and 4 anonymous splitters): Delete. (*anddi3_2rld, *anddi3_2rld_dot, *anddi3_2rld_dot2): New. (and<mode>3 for BOOL_128): Remove clobber. (*and<mode>3_internal for BOOL_128): Remove clobber. Adjust call of rs6000_split_logical. (*bool<mode>3_internal for BOOL_128): Adjust call of rs6000_split_logical. (*boolc<mode>3_internal1 for BOOL_128, *boolc<mode>3_internal2 for BOOL_128, *boolcc<mode>3_internal1 for BOOL_128, *boolcc<mode>3_internal2 for BOOL_128, *eqv<mode>3_internal1 for BOOL_128, *eqv<mode>3_internal2 for BOOL_128, *one_cmpl<mode>3_internal for BOOL_128): Ditto. * config/rs6000/vector.md (*vec_reload_and_plus_<mptrsize): Remove clobber. (*vec_reload_and_reg_<mptrsize>): Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214080 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-08-11 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-08-111-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/constraints.md (wh constraint): New constraint, for FP registers if direct move is available. (wi constraint): New constraint, for VSX/FP registers that can handle 64-bit integers. (wj constraint): New constraint for VSX/FP registers that can handle 64-bit integers for direct moves. (wk constraint): New constraint for VSX/FP registers that can handle 64-bit doubles for direct moves. (wy constraint): Make documentation match implementation. * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add scalar_in_vmx_p field to simplify tests of whether SFmode or DFmode can go in the Altivec registers. (rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p field, and wh/wi/wj/wk constraints. (rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and the wh/wi/wj/wk constraints. (rs6000_preferred_reload_class): If SFmode/DFmode can go in the upper registers, prefer VSX registers unless the operation is a memory operation with REG+OFFSET addressing. * config/rs6000/vsx.md (VSr mode attribute): Add support for DImode. Change SFmode to use ww constraint instead of d to allow SF registers in the upper registers. (VSr2): Likewise. (VSr3): Likewise. (VSr5): Fix thinko in comment. (VSa): New mode attribute that is an alternative to wa, that returns the VSX register class that a mode can go in, but may not be the preferred register class. (VS_64dm): New mode attribute for appropriate register classes for referencing 64-bit elements of vectors for direct moves and normal moves. (VS_64reg): Likewise. (vsx_mov<mode>): Change wa constraint to <VSa> to limit the register allocator to only registers the data type can handle. (vsx_le_perm_load_<mode>): Likewise. (vsx_le_perm_store_<mode>): Likewise. (vsx_xxpermdi2_le_<mode>): Likewise. (vsx_xxpermdi4_le_<mode>): Likewise. (vsx_lxvd2x2_le_<mode>): Likewise. (vsx_lxvd2x4_le_<mode>): Likewise. (vsx_stxvd2x2_le_<mode>): Likewise. (vsx_add<mode>3): Likewise. (vsx_sub<mode>3): Likewise. (vsx_mul<mode>3): Likewise. (vsx_div<mode>3): Likewise. (vsx_tdiv<mode>3_internal): Likewise. (vsx_fre<mode>2): Likewise. (vsx_neg<mode>2): Likewise. (vsx_abs<mode>2): Likewise. (vsx_nabs<mode>2): Likewise. (vsx_smax<mode>3): Likewise. (vsx_smin<mode>3): Likewise. (vsx_sqrt<mode>2): Likewise. (vsx_rsqrte<mode>2): Likewise. (vsx_tsqrt<mode>2_internal): Likewise. (vsx_fms<mode>4): Likewise. (vsx_nfma<mode>4): Likewise. (vsx_eq<mode>): Likewise. (vsx_gt<mode>): Likewise. (vsx_ge<mode>): Likewise. (vsx_eq<mode>_p): Likewise. (vsx_gt<mode>_p): Likewise. (vsx_ge<mode>_p): Likewise. (vsx_xxsel<mode>): Likewise. (vsx_xxsel<mode>_uns): Likewise. (vsx_copysign<mode>3): Likewise. (vsx_float<VSi><mode>2): Likewise. (vsx_floatuns<VSi><mode>2): Likewise. (vsx_fix_trunc<mode><VSi>2): Likewise. (vsx_fixuns_trunc<mode><VSi>2): Likewise. (vsx_x<VSv>r<VSs>i): Likewise. (vsx_x<VSv>r<VSs>ic): Likewise. (vsx_btrunc<mode>2): Likewise. (vsx_b2trunc<mode>2): Likewise. (vsx_floor<mode>2): Likewise. (vsx_ceil<mode>2): Likewise. (vsx_<VS_spdp_insn>): Likewise. (vsx_xscvspdp): Likewise. (vsx_xvcvspuxds): Likewise. (vsx_float_fix_<mode>2): Likewise. (vsx_set_<mode>): Likewise. (vsx_extract_<mode>_internal1): Likewise. (vsx_extract_<mode>_internal2): Likewise. (vsx_extract_<mode>_load): Likewise. (vsx_extract_<mode>_store): Likewise. (vsx_splat_<mode>): Likewise. (vsx_xxspltw_<mode>): Likewise. (vsx_xxspltw_<mode>_direct): Likewise. (vsx_xxmrghw_<mode>): Likewise. (vsx_xxmrglw_<mode>): Likewise. (vsx_xxsldwi_<mode>): Likewise. (vsx_xscvdpspn): Tighten constraints to only use register classes the types use. (vsx_xscvspdpn): Likewise. (vsx_xscvdpspn_scalar): Likewise. * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi, wj, and wk constraints. (GPR_REG_CLASS_P): New helper macro for register classes targeting general purpose registers. * config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode direct moves. (zero_extendsidi2_lfiwz): Use wj constraint for direct move of DImode instead of wm. Use wk constraint for direct move of DFmode instead of wm. (extendsidi2_lfiwax): Likewise. (lfiwax): Likewise. (lfiwzx): Likewise. (movdi_internal64): Likewise. * doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and wk constraints. Make the wy constraint documentation match them implementation. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213834 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2014-03-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (wD constraint): New constraint to match the constant integer to get the top DImode/DFmode out of a vector in a VSX register. * config/rs6000/predicates.md (vsx_scalar_64bit): New predicate to match the constant integer to get the top DImode/DFmode out of a vector in a VSX register. * config/rs6000/rs6000-builtins.def (VBPERMQ): Add vbpermq builtin for ISA 2.07. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add vbpermq builtins. * config/rs6000/rs6000.c (rs6000_debug_reg_global): If -mdebug=reg, print value of VECTOR_ELEMENT_SCALAR_64BIT. * config/rs6000/vsx.md (vsx_extract_<mode>, V2DI/V2DF modes): Optimize vec_extract of 64-bit values, where the value being extracted is in the top word, where we can use scalar instructions. Add direct move and store support. Combine the big endian/little endian vector select load support into a single insn. (vsx_extract_<mode>_internal1): Likewise. (vsx_extract_<mode>_internal2): Likewise. (vsx_extract_<mode>_load): Likewise. (vsx_extract_<mode>_store): Likewise. (vsx_extract_<mode>_zero): Delete, big and little endian insns are combined into vsx_extract_<mode>_load. (vsx_extract_<mode>_one_le): Likewise. * config/rs6000/rs6000.h (VECTOR_ELEMENT_SCALAR_64BIT): Macro to define the top 64-bit vector element. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wD constraint. PR target/60672 * config/rs6000/altivec.h (vec_xxsldwi): Add missing define to enable use of xxsldwi and xxpermdi builtin functions. (vec_xxpermdi): Likewise. * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Document use of vec_xxsldwi and vec_xxpermdi builtins. [gcc/testsuite] 2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p8vector-vbpermq.c: New test to test the vbpermq builtin. * gcc.target/powerpc/vsx-extract-1.c: New test to test VSX vec_select optimizations. * gcc.target/powerpc/vsx-extract-2.c: Likewise. * gcc.target/powerpc/vsx-extract-3.c: Likewise. PR target/60672 * gcc.target/powerpc/pr60676.c: New file, make sure xxsldwi and xxpermdi builtins are supported. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208877 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-03-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>wschmidt2014-03-031-0/+3
| | | | | | | | * config/rs6000/constraints.md: Document reserved use of "wc". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208266 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years in gcc/rsandifo2014-01-021-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206289 138bc75d-0d04-0410-961f-82ee72b054a4
* 2013-09-20 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2013-09-231-24/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new constraints: wu, ww, and wy. Repurpose wv constraint added during power8 changes. Put wg constraint in alphabetical order. * config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch for future work to add ISA 2.07 VSX single precision support. (-mvsx-scalar-double): Change default from -1 to 1, update documentation comment. (-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df. (-mupper-regs-df): New debug switch to control whether DF values can go in the traditional Altivec registers. (-mupper-regs-sf): New debug switch to control whether SF values can go in the traditional Altivec registers. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww, and wy constraints. (rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df. Add new constraints, wu/ww/wy. Repurpose wv constraint. (rs6000_debug_legitimate_address_p): Print if we are running before, during, or after reload. (rs6000_secondary_reload): Add a comment. (rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf. * config/rs6000/constraints.md (wa constraint): Sort w<x> constraints. Update documentation string. (wd constraint): Likewise. (wf constraint): Likewise. (wg constraint): Likewise. (wn constraint): Likewise. (ws constraint): Likewise. (wt constraint): Likewise. (wx constraint): Likewise. (wz constraint): Likewise. (wu constraint): New constraint for ISA 2.07 SFmode scalar instructions. (ww constraint): Likewise. (wy constraint): Likewise. (wv constraint): Repurpose ISA 2.07 constraint that we not used in the previous submissions. * doc/md.texi (PowerPC and IBM RS6000): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202843 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2013-05-221-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add documentation for the power8 crypto builtins. * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md. * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support macros for defining power8 builtin functions. (BU_P8V_AV_2): Likewise. (BU_P8V_AV_P): Likewise. (BU_P8V_VSX_1): Likewise. (BU_P8V_OVERLOAD_1): Likewise. (BU_P8V_OVERLOAD_2): Likewise. (BU_CRYPTO_1): Likewise. (BU_CRYPTO_2): Likewise. (BU_CRYPTO_3): Likewise. (BU_CRYPTO_OVERLOAD_1): Likewise. (BU_CRYPTO_OVERLOAD_2): Likewise. (XSCVSPDP): Fix typo, point to the correct instruction. (VCIPHER): Add power8 crypto builtins. (VCIPHERLAST): Likewise. (VNCIPHER): Likewise. (VNCIPHERLAST): Likewise. (VPMSUMB): Likewise. (VPMSUMH): Likewise. (VPMSUMW): Likewise. (VPERMXOR_V2DI): Likewise. (VPERMXOR_V4SI: Likewise. (VPERMXOR_V8HI: Likewise. (VPERMXOR_V16QI: Likewise. (VSHASIGMAW): Likewise. (VSHASIGMAD): Likewise. (VPMSUM): Likewise. (VPERMXOR): Likewise. (VSHASIGMA): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define __CRYPTO__ if the crypto instructions are available. (altivec_overloaded_builtins): Add support for overloaded power8 builtins. * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add support for power8 crypto builtins. (builtin_function_type): Likewise. (altivec_init_builtins): Add support for builtins that take vector long long (V2DI) arguments. * config/rs6000/crypto.md: New file, define power8 crypto instructions. 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * doc/invoke.texi (Option Summary): Add power8 options. (RS/6000 and PowerPC Options): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use constraints.md instead of rs6000.h. Reorder w* constraints. Add wm, wn, wr documentation. * gcc/config/rs6000/constraints.md (wm): New constraint for VSX registers if direct move instructions are enabled. (wn): New constraint for no registers. (wq): New constraint for quad word even GPR registers. (wr): New constraint if 64-bit instructions are enabled. (wv): New constraint if power8 vector instructions are enabled. (wQ): New constraint for quad word memory locations. * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New constraint for 0..15 for crypto instructions. (gpc_reg_operand): If VSX allow registers in VSX registers as well as GPR and floating point registers. (int_reg_operand): New predicate to match only GPR registers. (base_reg_operand): New predicate to match base registers. (quad_int_reg_operand): New predicate to match even GPR registers for quad memory operations. (vsx_reg_or_cint_operand): New predicate to allow vector logical operations in both GPR and VSX registers. (quad_memory_operand): New predicate for quad memory operations. (reg_or_indexed_operand): New predicate for direct move support. * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS. (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8). (POWERPC_MASKS): Add power8 options. (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the various options. * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8. * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation. (-mpower8-fusion): New power8 options. (-mpower8-fusion-sign): Likewise. (-mpower8-vector): Likewise. (-mcrypto): Likewise. (-mdirect-move): Likewise. (-mquad-memory): Likewise. * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for power8. (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR registers. (rs6000_debug_reg_print): Print the base register class if -mdebug=reg. (rs6000_debug_vector_unit): Add p8_vector. (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint definitions. Also print fusion state. (rs6000_init_hard_regno_mode_ok): Set up power8 constraints. (rs6000_builtin_mask_calculate): Add power8 builtin support. (rs6000_option_override_internal): Add support for power8. (rs6000_common_init_builtins): Add debugging for skipped builtins if -mdebug=builtin. (rs6000_adjust_cost): Add power8 support. (rs6000_issue_rate): Likewise. (insn_must_be_first_in_group): Likewise. (insn_must_be_last_in_group): Likewise. (force_new_group): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a power8 capable assembler, default to power7 options. (TARGET_DIRECT_MOVE): Likewise. (TARGET_CRYPTO): Likewise. (TARGET_P8_VECTOR): Likewise. (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support. (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise. (VECTOR_MEM_P8_VECTOR_P): Likewise. (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise. (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise. (TARGET_XSCVDPSPN): Likewise. (TARGET_XSCVSPDPN): Likewsie. (TARGET_SYNC_HI_QI): Likewise. (TARGET_SYNC_TI): Likewise. (MASK_CRYPTO): Likewise. (MASK_DIRECT_MOVE): Likewise. (MASK_P8_FUSION): Likewise. (MASK_P8_VECTOR): Likewise. (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the TFmode temporary used by some of the direct move instructions to get two FP temporary registers does not force creation of a stack frame. (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs. (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so that any VSX registers are tieable, even if they are also an Altivec vector mode. (r6000_reg_class_enum): Add wm, wr, wv constraints. (RS6000_BTM_P8_VECTOR): Power8 builtin support. (RS6000_BTM_CRYPTO): Likewise. (RS6000_BTM_COMMON): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power8. * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise. (enum rs6000_vector): Add power8 vector support. [gcc/testsuite] 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8 crypto builtins. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@199217 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2013-03-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2013-03-20 Pat Haugen <pthaugen@us.ibm.com> * config/rs6000/predicates.md (indexed_address, update_address_mem update_indexed_address_mem): New predicates. * config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type" attribute for load/store instructions. * config/rs6000/dfp.md (movsd_store): Likewise. (movsd_load): Likewise. * config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise. (unnamed HI->DI extend define_insn): Likewise. (unnamed SI->DI extend define_insn): Likewise. (unnamed QI->SI extend define_insn): Likewise. (unnamed QI->HI extend define_insn): Likewise. (unnamed HI->SI extend define_insn): Likewise. (unnamed HI->SI extend define_insn): Likewise. (extendsfdf2_fpr): Likewise. (movsi_internal1): Likewise. (movsi_internal1_single): Likewise. (movhi_internal): Likewise. (movqi_internal): Likewise. (movcc_internal1): Correct mnemonic for stw insn. Set correct "type" attribute for load/store instructions. (mov<mode>_hardfloat): Set correct "type" attribute for load/store instructions. (mov<mode>_softfloat): Likewise. (mov<mode>_hardfloat32): Likewise. (mov<mode>_hardfloat64): Likewise. (mov<mode>_softfloat64): Likewise. (movdi_internal32): Likewise. (movdi_internal64): Likewise. (probe_stack_<mode>): Likewise. 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary floating point, and decimal floating point to reload iterator. * config/rs6000/constraints.md (wl constraint): New constraints to return FLOAT_REGS if certain options are used to reduce the number of separate patterns that exist in the file. (wx constraint): Likewise. (wz constraint): Likewise. * config/rs6000/rs6000.c (rs6000_debug_reg_global): If -mdebug=reg, print wg, wl, wx, and wz constraints. (rs6000_init_hard_regno_mode_ok): Initialize new constraints. Initialize the reload functions for 64-bit binary/decimal floating point types. (reg_offset_addressing_ok_p): If we are on a power7 or later, use LFIWZX and STFIWX to load/store 32-bit decimal types, and don't create the buffer on the stack to overcome not having a 32-bit load and store. (rs6000_emit_move): Likewise. (rs6000_secondary_memory_needed_rtx): Likewise. (rs6000_alloc_sdmode_stack_slot): Likewise. (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f via xxlxor, just like DFmode 0.0. * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro, define as 1 if we are running on a power7 or newer. (enum r6000_reg_class_enum): Add new constraints. * config/rs6000/dfp.md (movsd): Delete, combine with binary floating point moves in rs6000.md. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). Use LFIWZX and STFIWX for loading SDmode on power7. Use xxlxor to create 0.0f. (movsd splitter): Likewise. (movsd_hardfloat): Likewise. (movsd_softfloat): Likewise. * config/rs6000/rs6000.md (FMOVE32): New iterators to combine binary and decimal floating point moves. (fmove_ok): New attributes to combine binary and decimal floating point moves, and to combine power6x (mfpgpr) moves along normal floating moves. (real_value_to_target): Likewise. (f32_lr): Likewise. (f32_lm): Likewise. (f32_li): Likewise. (f32_sr): Likewise. (f32_sm): Likewise. (f32_si): Likewise. (movsf): Combine binary and decimal floating point moves. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). Use LFIWZX and STFIWX for loading SDmode on power7. (mov<mode> for SFmode/SDmode); Likewise. (SFmode/SDmode splitters): Likewise. (movsf_hardfloat): Likewise. (mov<mode>_hardfloat for SFmode/SDmode): Likewise. (movsf_softfloat): Likewise. (mov<mode>_softfloat for SFmode/SDmode): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl, wx and wz constraints. * config/rs6000/constraints.md (wg constraint): New constraint to return FLOAT_REGS if -mmfpgpr (power6x) was used. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg constraint. * config/rs6000/rs6000.c (rs6000_debug_reg_global): If -mdebug=reg, print wg, wl, wx, and wz constraints. (rs6000_init_hard_regno_mode_ok): Initialize new constraints. Initialize the reload functions for 64-bit binary/decimal floating point types. (reg_offset_addressing_ok_p): If we are on a power7 or later, use LFIWZX and STFIWX to load/store 32-bit decimal types, and don't create the buffer on the stack to overcome not having a 32-bit load and store. (rs6000_emit_move): Likewise. (rs6000_secondary_memory_needed_rtx): Likewise. (rs6000_alloc_sdmode_stack_slot): Likewise. (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f via xxlxor, just like DFmode 0.0. * config/rs6000/dfp.md (movdd): Delete, combine with binary floating point moves in rs6000.md. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). Use LFIWZX and STFIWX for loading SDmode on power7. (movdd splitters): Likewise. (movdd_hardfloat32): Likewise. (movdd_softfloat32): Likewise. (movdd_hardfloat64_mfpgpr): Likewise. (movdd_hardfloat64): Likewise. (movdd_softfloat64): Likewise. * config/rs6000/rs6000.md (FMOVE64): New iterators to combine 64-bit binary and decimal floating point moves. (FMOVE64X): Likewise. (movdf): Combine 64-bit binary and decimal floating point moves. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). (mov<mode> for DFmode/DDmode): Likewise. (DFmode/DDmode splitters): Likewise. (movdf_hardfloat32): Likewise. (mov<mode>_hardfloat32 for DFmode/DDmode): Likewise. (movdf_softfloat32): Likewise. (movdf_hardfloat64_mfpgpr): Likewise. (movdf_hardfloat64): Likewise. (mov<mode>_hardfloat64 for DFmode/DDmode): Likewise. (movdf_softfloat64): Likewise. (mov<mode>_softfloat64 for DFmode/DDmode): Likewise. (reload_<mode>_load): Move to later in the file so they aren't in the middle of the floating point move insns. (reload_<mode>_store): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg constraint. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg constraint if -mdebug=reg. (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if -mfpgpr. Enable using dd reload support if needed. * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit binary and decimal floating point moves in rs6000.md. (movtd_internal): Likewise. * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and decimal floating point moves. (movtf): Likewise. (movtf_internal): Likewise. (mov<mode>_internal, TDmode/TFmode): Likewise. (movtf_softfloat): Likewise. (mov<mode>_softfloat, TDmode/TFmode): Likewise. * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with movdi_internal64, using wg constraint for move direct operations. (movdi_internal64): Likewise. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print MODES_TIEABLE_P for selected modes. Print the numerical value of the various virtual registers. Use GPR/FPR first/last values, instead of hard coding the register numbers. Print which modes have reload functions registered. (rs6000_option_override_internal): If -mdebug=reg, trace the options settings before/after setting cpu, target and subtarget settings. (rs6000_secondary_reload_trace): Improve the RTL dump for -mdebug=addr and for secondary reload failures in rs6000_secondary_reload_inner. (rs6000_secondary_reload_fail): Likewise. (rs6000_secondary_reload_inner): Likewise. * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience macros for first/last GPR and FPR registers. (LAST_GPR_REGNO): Likewise. (FIRST_FPR_REGNO): Likewise. (LAST_FPR_REGNO): Likewise. * config/rs6000/vector.md (mul<mode>3): Use the combined macro VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P. (vcond<mode><mode>): Likewise. (vcondu<mode><mode>): Likewise. (vector_gtu<mode>): Likewise. (vector_gte<mode>): Likewise. (xor<mode>3): Don't allow logical operations on TImode in 32-bit to prevent the compiler from converting DImode operations to TImode. (ior<mode>3): Likewise. (and<mode>3): Likewise. (one_cmpl<mode>2): Likewise. (nor<mode>3): Likewise. (andc<mode>3): Likewise. * config/rs6000/constraints.md (wt constraint): New constraint that returns VSX_REGS if TImode is allowed in VSX registers. * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy constant under VSX. * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is similar to TImode, but it is restricted to being in the GPRs. * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow TImode to occupy a single VSX register. * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to -mvsx-timode for power7/power8. (power7 cpu): Likewise. (power8 cpu): Likewise. * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make sure that TFmode/TDmode take up two registers if they are ever allowed in the upper VSX registers. (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX registers. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_debug_reg_global): Add debugging for PTImode and wt constraint. Print if LRA is turned on. (rs6000_option_override_internal): Give an error if -mvsx-timode and VSX is not enabled. (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode to reg+offset addressing. Use PTImode when checking offset addresses for validity. (reg_offset_addressing_ok_p): Likewise. (rs6000_legitimate_offset_address_p): Likewise. (rs6000_legitimize_address): Likewise. (rs6000_legitimize_reload_address): Likewise. (rs6000_legitimate_address_p): Likewise. (rs6000_eliminate_indexed_memrefs): Likewise. (rs6000_emit_move): Likewise. (rs6000_secondary_reload): Likewise. (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit reloads to fpr registers to continue to use reg+offset addressing, but 64-bit reloads to altivec registers need reg+reg addressing. Drop test for PRE_MODIFY, since VSX loads/stores no longer support it. Treat LO_SUM like a PLUS operation. (rs6000_secondary_reload_class): If type is 64-bit, prefer to use FLOAT_REGS instead of VSX_RGS to allow use of reg+offset addressing. (rs6000_cannot_change_mode_class): Do not allow TImode in VSX registers to share a register with a smaller sized type, since VSX puts scalars in the upper 64-bits. (print_operand): Add support for PTImode. (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX registers, but don't have arithmetic support. (rs6000_memory_move_cost): Add test for VSX. (rs6000_opt_masks): Add -mvsx-timode. * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves for TImode. (VSs): Likewise. (VSr): Use wt constraint for TImode. (VSv): Drop TImode support. (vsx_movti): Delete, replace with versions for 32-bit and 64-bit. (vsx_movti_64bit): Likewise. (vsx_movti_32bit): Likewise. (vec_store_<mode>): Use VSX iterator instead of vector iterator. (vsx_and<mode>3): Delete use of '?' constraint on inputs, just put one '?' on the appropriate output constraint. Do not allow TImode logical operations on 32-bit systems. (vsx_ior<mode>3): Likewise. (vsx_xor<mode>3): Likewise. (vsx_one_cmpl<mode>2): Likewise. (vsx_nor<mode>3): Likewise. (vsx_andc<mode>3): Likewise. (vsx_concat_<mode>): Likewise. (vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes. * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from OPTION_MASK_VSX_TIMODE. (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt. (STACK_SAVEAREA_MODE): Use PTImode instead of TImode. * config/rs6000/rs6000.md (INT mode attribute): Add PTImode. (TI2 iterator): New iterator for TImode, PTImode. (wd mode attribute): Add values for vector types. (movti_string): Replace TI move operations with operations for TImode and PTImode. Add support for TImode being allowed in VSX registers. (mov<mode>_string, TImode/PTImode): Likewise. (movti_ppc64): Likewise. (mov<mode>_ppc64, TImode/PTImode): Likewise. (TI mode splitters): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt constraint. [gcc/testsuite] 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/mmfpgpr.c: New test. * gcc.target/powerpc/sd-vsx.c: Likewise. * gcc.target/powerpc/sd-pwr6.c: Likewise. * gcc.target/powerpc/vsx-float0.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196831 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years in gcc/rsandifo2013-01-101-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195098 138bc75d-0d04-0410-961f-82ee72b054a4
* 2012-07-27 Segher Boessenkool <segher@kernel.crashing.org>segher2012-07-271-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/constraints.md: Delete "q" constraint. * config/rs6000/dfp.md (movsd_hardfloat, movsd_softfloat): Delete the "q" alternative. * config/rs6000/predicates.md (gpc_reg_operand): Adjust. * config/rs6000/rs6000.c (rs6000_debug_reg_global, rs6000_init_hard_regno_mode_ok, rs6000_dbx_register_number): Adjust to MQ_REGNO removal. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Adjust comment. (REG_ALLOC_ORDER): Adjust comment. Remove MQ from alloc order. (enum reg_class): Adjust comment. Delete MQ_REGS. (REG_CLASS_CONTENTS): Adjust. (REGISTER_NAMES, ADDITIONAL_REGISTER_NAMES): Adjust comment. * config/rs6000/rs6000.md: Delete MQ_REGNO. (movsi_internal1, movsi_internal1_single, movhi_internal, movqi_internal, movcc_internal1, movsf_hardfloat, movsf_softfloat): Delete the "q" alternative. (ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5, ctr<mode>_internal6): Delete "q" constraint. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@189913 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/53914amodra2012-07-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR target/54009 * config/rs6000/constraints.md (Y): Use mem_operand_gpr. * config/rs6000/predicates.md (word_offset_memref_operand): Delete. Adjust all rs6000_legitimate_offset_address_p calls. * config/rs6000/rs6000-protos.h (mem_operand_gpr): Declare. (rs6000_secondary_reload_gpr): Declare. (rs6000_legitimate_offset_address_p): Update prototype. (rs6000_offsettable_memref_p): Delete. (rs6000_secondary_reload_ppc64): Delete. * config/rs6000/rs6000.c (address_offset): New function. (mem_operand_gpr): Likewise. (rs6000_legitimate_offset_address_p): Add worst_case param. When not worst_case assume class of regs with least restrictive offsets. Adjust all calls. (legitimate_lo_sum_address_p): Simplify register mode tests. (rs6000_legitimize_address): Likewise. Assume best case offset addressing. Combine ELF and MACHO lo_sum code. (rs6000_mode_dependent_address): Correct offset addressing limits. (rs6000_offsettable_memref_p): Make static, add reg_mode param. Use reg_mode to help rs6000_legitimate_offset_address_p. (rs6000_secondary_reload): Use address_offset. Handle 32-bit multi gpr load/store when offset too large. (rs6000_secondary_reload_gpr): Renamed rs6000_secondary_reload_ppc64. (rs6000_split_multireg_move): Adjust rs6000_offsettable_memref_p calls. * config/rs6000/rs6000.md (movdf_hardfloat32): Use 'Y' constraint for gpr load/store. Order alternatives as r->Y,Y->r,r->r and d->m,m->d,d->d. Correct size of gpr load/store. (movdf_softfloat32): Use 'Y' constraint for gpr load/store. Order alternatives. (movti_ppc64): Likewise. (movdi_internal32): Likewise. Also disparage fprs. (movdi_mfpgpr, movdi_internal64): Likewise. (movtf_internal): Use 'm' for fpr load/store. Order alternatives. (movtf_softfloat): Order alternatives. (extenddftf2_internal): Use 'm' and 'Y' for store. (movti_power, movti_string): Use 'Y' for gpr load/store. Order. (stack_protect_setdi, stack_protect_testdi): Likewise. (movdf_hardfloat64_mfpgpr, movdf_hardfloat64): Order alternatives. (movdf_softfloat64): Likewise. (reload_<mode>_store): Adjust reload_di_store to provide reload_si_store as well. (reload_<mode>_load): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@189801 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/rsandifo2011-09-141-1/+1
| | | | | | | | | * config/rs6000/rs6000.md: Use match_test rather than eq/ne symbol_ref throughout file. * config/rs6000/constraints.md: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178866 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/48032amodra2011-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | * config/rs6000/rs6000.c (offsettable_ok_by_alignment): Do not presume symbol_refs without a symbol_ref_decl are suitably aligned, nor other trees we may see here. Handle anchor symbols. (legitimate_constant_pool_address_p): Comment. Add mode param. Check cmodel=medium addresses. Adjust all calls. (rs6000_emit_move): Don't call offsettable_ok_by_alignment on creating cmodel=medium optimized access to locals. * config/rs6000/constraints.md (R): Pass QImode to legitimate_constant_pool_address_p. * config/rs6000/predicates.md (input_operand): Pass mode to legitimate_constant_pool_address_p. * config/rs6000/rs6000-protos.h (legitimate_constant_pool_address_p): Update prototype. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@170976 138bc75d-0d04-0410-961f-82ee72b054a4
* * doc/invoke.texi: Add mcmodel to powerpc options.amodra2010-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * configure.ac: Add HAVE_LD_LARGE_TOC test. * configure: Regenerate. * config.in: Regenerate. * config/rs6000/linux64.opt (mcmodel): New. * config/rs6000/linux64.h (TARGET_USES_LINUX64_OPT): Define. (TARGET_CMODEL): Define. (SUBSUBTARGET_OVERRIDE_OPTIONS): Check user -mcmodel choice, select CMODEL_MEDIUM default. * config/rs6000/rs6000.h (enum rs6000_cmodel): New. (TARGET_CMODEL): Define default. * config/rs6000/rs6000.c (cmodel): New variable. (rs6000_explicit_options): Add cmodel field. (rs6000_handle_option): Handle -mcmodel. (create_TOC_reference): Add largetoc_reg param. Generate high, lo_sum rtl for CMODEL_MEDIUM and CMODEL_LARGE. Update all callers. (rs6000_delegitimize_address): Recognise new toc reference rtl and minimal-toc rtl. (rs6000_legitimize_reload_address): Handle new toc references. (print_operand_address): Handle legitimate_constant_pool_address_p match before lo_sum. (rs6000_eliminate_indexed_memrefs): Tidy. (rs6000_emit_move): Tweak threshold for inlining constants. Keep rs6000_emit_allocate_stack large stack frame offsets loaded into r0 inline. (rs6000_generate_compare <cmptf_internal2>): One more clobber. (tocrel_base, tocrel_offset): New variables. (toc_relative_expr_p): Set them here. (print_operand_address): Skip over any offset on constant pool address. (rs6000_output_addr_const_extra): Print tocrel_offset before @toc. (rs6000_mode_dependent_address <LO_SUM>): False for new toc refs. (offsettable_ok_by_alignment): New function. (rs6000_emit_move): Address suitably aligned local symbol_refs relative to the toc pointer for -mcmodel=medium. (legitimate_constant_pool_address_p): Make param const_rtx. Add strict param. Allow lo_sum version of addressing. Verify reg used for -mminimal-toc and -mcmodel != small. Update all callers. * config/rs6000/constraints.md: Update for above change. * config/rs6000/predicates.md: Likewise. * config/rs6000/rs6000.md (tls_gd_aix): Generate -mcmodel=medium/large code. (tls_gd): Split for -mcmodel=medium/large. (tls_gd_high, tls_gd_low): New. (tls_ld_aix, tls_ld, tls_ld_high, tls_ld_low): Similarly. (tls_got_dtprel, tls_got_dtprel_high, tls_got_dtprel_low): Similarly. (tls_got_tprel, tls_got_tprel_high, tls_got_tprel_low): Similarly. (largetoc_high, largetoc_low): New. (cmptf_internal2): Add clobber. * config/rs6000/rs6000-protos.h: Update. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@160773 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-05-28 Segher Boessenkool <segher@kernel.crashing.org>segher2010-05-271-1/+1
| | | | | | | | | | | | | | | | | | * config/rs6000/constraints.md ("z" constraint): Change to CA_REGS. * config/rs6000/predicates.md: Change XER_REGNO_P to CA_REGNO_P throughout. * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Change "xer" to "ca". Change XER_REGNO_P to CA_REGNO_P, XER_REGNO to CA_REGNO, and XER_REGS to CA_REGS throughout. * config/rs6000/rs6000.h: Same. (ADDITIONAL_REGISTER_NAMES): Add "xer". * config/rs6000/rs6000.md: Change XER_REGNO to CA_REGNO. Document that mode_iterator "P" is the size for arithmetic carries as well. * doc/md.texi (rs6000 section, "z" constraint): Fix documentation. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159953 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright yearmeissner2010-03-241-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@157713 138bc75d-0d04-0410-961f-82ee72b054a4
* Commit patch #3 of 4 for Power7 VSX supportmeissner2009-07-231-4/+30
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150018 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/rsandifo2009-07-181-2/+12
| | | | | | | | | | | | | | | | * doc/md.texi: Document the new PowerPC "es" constraint. Document that "m" can include automodified addresses on this target, and explain how %U must be used. Extend the "Q" and "Z" documentation to suggest "es" as well as "m". * config/rs6000/constraints.md (es): New memory constraint. (Q, Z): Update strings to match new documentation. gcc/testsuite/ * gcc.target/powerpc/asm-es-1.c: New test. * gcc.target/powerpc/asm-es-2.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@149766 138bc75d-0d04-0410-961f-82ee72b054a4
* Create new constraint "d" for PowerPC FPRs with 64-bit values.eager2009-06-171-0/+4
| | | | | | | | Replace uses of "f" constraint with "d" as needed. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@148630 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/host-hpux.c: Change copyright header to refer to version 3 of the GNUnickc2007-08-021-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General Public License and to point readers at the COPYING3 file and the FSF's license web page. * config/alpha/predicates.md, config/alpha/vms-ld.c, config/alpha/linux.h, config/alpha/alpha.opt, config/alpha/linux-elf.h, config/alpha/vms.h, config/alpha/elf.h, config/alpha/vms-unwind.h, config/alpha/ev4.md, config/alpha/ev6.md, config/alpha/alpha.c, config/alpha/vms-cc.c, config/alpha/alpha.h, config/alpha/sync.md, config/alpha/openbsd.h, config/alpha/alpha.md, config/alpha/alpha-modes.def, config/alpha/ev5.md, config/alpha/alpha-protos.h, config/alpha/freebsd.h, config/alpha/osf5.h, config/alpha/netbsd.h, config/alpha/vms64.h, config/alpha/constraints.md, config/alpha/osf.h, config/alpha/xm-vms.h, config/alpha/unicosmk.h, config/linux.h, config/frv/predicates.md, config/frv/frv.h, config/frv/linux.h, config/frv/frv.md, config/frv/frv.opt, config/frv/frv-modes.def, config/frv/frv-asm.h, config/frv/frv-protos.h, config/frv/frv-abi.h, config/frv/frv.c, config/s390/tpf.h, config/s390/s390.c, config/s390/predicates.md, config/s390/s390.h, config/s390/linux.h, config/s390/tpf.md, config/s390/tpf.opt, config/s390/2064.md, config/s390/2084.md, config/s390/s390.md, config/s390/s390.opt, config/s390/s390-modes.def, config/s390/fixdfdi.h, config/s390/constraints.md, config/s390/s390-protos.h, config/s390/s390x.h, config/elfos.h, config/dbxcoff.h, config/m32c/predicates.md, config/m32c/cond.md, config/m32c/m32c.c, config/m32c/minmax.md, config/m32c/blkmov.md, config/m32c/m32c-pragma.c, config/m32c/m32c.h, config/m32c/prologue.md, config/m32c/m32c.abi, config/m32c/muldiv.md, config/m32c/bitops.md, config/m32c/mov.md, config/m32c/addsub.md, config/m32c/m32c.md, config/m32c/m32c.opt, config/m32c/t-m32c, config/m32c/m32c-modes.def, config/m32c/jump.md, config/m32c/shift.md, config/m32c/m32c-protos.h, config/libgloss.h, config/spu/spu-protos.h, config/spu/predicates.md, config/spu/spu-builtins.h, config/spu/spu.c, config/spu/spu-builtins.def, config/spu/spu-builtins.md, config/spu/spu.h, config/spu/spu-elf.h, config/spu/constraints.md, config/spu/spu.md, config/spu/spu-c.c, config/spu/spu.opt, config/spu/spu-modes.def, config/spu/t-spu-elf, config/interix.h, config/sparc/hypersparc.md, config/sparc/predicates.md, config/sparc/linux.h, config/sparc/sp64-elf.h, config/sparc/supersparc.md, config/sparc/cypress.md, config/sparc/openbsd1-64.h, config/sparc/openbsd64.h, config/sparc/niagara.md, config/sparc/sparc.md, config/sparc/long-double-switch.opt, config/sparc/ultra3.md, config/sparc/sparc.opt, config/sparc/sync.md, config/sparc/sp-elf.h, config/sparc/sparc-protos.h, config/sparc/ultra1_2.md, config/sparc/biarch64.h, config/sparc/sparc.c, config/sparc/little-endian.opt, config/sparc/sysv4-only.h, config/sparc/sparc.h, config/sparc/linux64.h, config/sparc/freebsd.h, config/sparc/sol2.h, config/sparc/rtemself.h, config/sparc/netbsd-elf.h, config/sparc/vxworks.h, config/sparc/sparc-modes.def, config/sparc/sparclet.md, config/sparc/sysv4.h, config/vx-common.h, config/netbsd-aout.h, config/flat.h, config/m32r/m32r.md, config/m32r/predicates.md, config/m32r/little.h, config/m32r/m32r.c, config/m32r/m32r.opt, config/m32r/linux.h, config/m32r/constraints.md, config/m32r/m32r.h, config/m32r/m32r-protos.h, config/vxworks.opt, config/darwin-c.c, config/darwin.opt, config/i386/i386.h, config/i386/cygming.h, config/i386/linux.h, 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config/arc/arc.h, config/mcore/mcore-elf.h, config/mcore/mcore-protos.h, config/mcore/predicates.md, config/mcore/mcore.md, config/mcore/mcore.c, config/mcore/mcore.opt, config/mcore/mcore.h, config/mcore/mcore-pe.h, config/darwin.c, config/freebsd-nthr.h, config/score/predicates.md, config/score/score-version.h, config/score/score-protos.h, config/score/misc.md, config/score/elf.h, config/score/score.c, config/score/mac.md, config/score/score7.md, config/score/score.h, config/score/score-conv.h, config/score/score-mdaux.c, config/score/score.md, config/score/score.opt, config/score/score-modes.def, config/score/score-mdaux.h, config/score/mul-div.S, config/arm/uclinux-elf.h, config/arm/semi.h, config/arm/ecos-elf.h, config/arm/arm1020e.md, config/arm/symbian.h, config/arm/linux-elf.h, config/arm/arm1026ejs.md, config/arm/arm1136jfs.md, config/arm/elf.h, config/arm/aout.h, config/arm/arm.c, config/arm/thumb2.md, config/arm/vec-common.md, config/arm/coff.h, config/arm/strongarm-pe.h, config/arm/arm.h, config/arm/cortex-a8-neon.md, config/arm/semiaof.h, config/arm/cortex-a8.md, config/arm/uclinux-eabi.h, config/arm/arm-modes.def, config/arm/linux-eabi.h, config/arm/rtems-elf.h, config/arm/neon-schedgen.ml, config/arm/arm-cores.def, config/arm/arm-protos.h, config/arm/vfp.md, config/arm/aof.h, config/arm/linux-gas.h, config/arm/wince-pe.h, config/arm/neon.md, config/arm/constraints.md, config/arm/neon.ml, config/arm/xscale-elf.h, config/arm/strongarm-coff.h, config/arm/arm.opt, config/arm/arm926ejs.md, config/arm/predicates.md, config/arm/iwmmxt.md, config/arm/arm_neon.h, config/arm/unknown-elf.h, config/arm/kaos-arm.h, config/arm/bpabi.h, config/arm/pe.opt, config/arm/neon-testgen.ml, config/arm/arm.md, config/arm/xscale-coff.h, config/arm/pe.c, config/arm/arm-generic.md, config/arm/pe.h, config/arm/kaos-strongarm.h, config/arm/freebsd.h, config/arm/neon-docgen.ml, config/arm/netbsd.h, config/arm/fpa.md, config/arm/strongarm-elf.h, config/arm/cirrus.md, config/arm/netbsd-elf.h, config/arm/vxworks.h, config/arm/neon-gen.ml, config/kaos.h, config/darwin-driver.c, config/pa/predicates.md, config/pa/pa64-hpux.h, config/pa/pa-hpux.opt, config/pa/som.h, config/pa/pa-hpux1010.opt, config/pa/pa-hpux1111.opt, config/pa/pa-pro-end.h, config/pa/elf.h, config/pa/fptr.c, config/pa/pa64-linux.h, config/pa/pa.md, config/pa/pa.opt, config/pa/pa-hpux.h, config/pa/pa-hpux10.h, config/pa/pa-hpux11.h, config/pa/pa-hpux1010.h, config/pa/pa-protos.h, config/pa/pa-osf.h, config/pa/pa-hpux1111.h, config/pa/pa-64.h, config/pa/milli64.S, config/pa/pa.c, config/pa/pa-linux.h, config/pa/pa.h, config/pa/pa32-linux.h, config/pa/pa64-hpux.opt, config/pa/pa64-regs.h, config/pa/pa-modes.def, config/pa/constraints.md, config/darwin9.h, config/mips/4100.md, config/mips/linux.h, config/mips/elfoabi.h, config/mips/elf.h, config/mips/sdb.h, config/mips/windiss.h, config/mips/rtems.h, config/mips/3000.md, config/mips/iris5.h, config/mips/5000.md, config/mips/7000.md, config/mips/9000.md, config/mips/4600.md, config/mips/linux64.h, config/mips/elforion.h, config/mips/constraints.md, config/mips/generic.md, config/mips/predicates.md, config/mips/4300.md, config/mips/mips-ps-3d.md, config/mips/iris.h, config/mips/24k.md, config/mips/mips.md, config/mips/mips.opt, config/mips/4k.md, config/mips/5k.md, config/mips/vr4120-div.S, config/mips/openbsd.h, config/mips/iris6.h, config/mips/4000.md, config/mips/mips-protos.h, config/mips/6000.md, config/mips/mips.c, config/mips/mips.h, config/mips/r3900.h, config/mips/74k.md, config/mips/netbsd.h, config/mips/vxworks.h, config/mips/mips-modes.def, config/mips/vr.h, config/soft-fp/t-softfp, config/openbsd.h, config/ptx4.h, config/freebsd-spec.h, config/vax/vax.c, config/vax/openbsd.h, config/vax/vax.h, config/vax/elf.h, config/vax/vax.md, config/vax/bsd.h, config/vax/vax.opt, config/vax/vax-modes.def, config/vax/openbsd1.h, config/vax/netbsd.h, config/vax/vax-protos.h, config/vax/netbsd-elf.h, config/vax/vaxv.h, config/vax/ultrix.h, config/freebsd.h, config/h8300/rtems.h, config/h8300/predicates.md, config/h8300/h8300.c, config/h8300/h8300.h, config/h8300/elf.h, config/h8300/h8300.md, config/h8300/h8300.opt, config/h8300/coff.h, config/h8300/h8300-protos.h, config/v850/v850.md, config/v850/predicates.md, config/v850/v850-c.c, config/v850/v850.c, config/v850/v850.opt, config/v850/v850.h, config/v850/v850-protos.h, config/vxworks.c, config/knetbsd-gnu.h, config/sol2-6.h, config/vxworks.h, config/mmix/mmix.h, config/mmix/predicates.md, config/mmix/mmix-protos.h, config/mmix/mmix.md, config/mmix/mmix.c, config/mmix/mmix.opt, config/mmix/mmix-modes.def, config/bfin/bfin.opt, config/bfin/rtems.h, config/bfin/bfin-modes.def, config/bfin/predicates.md, config/bfin/bfin-protos.h, config/bfin/bfin.c, config/bfin/bfin.h, config/bfin/bfin.md: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@127157 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/rs6000/constraints.md: Add "W" constraint.dje2006-03-291-0/+4
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@112518 138bc75d-0d04-0410-961f-82ee72b054a4
* Remove extra parentheses for "M" case.dje2006-03-291-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@112512 138bc75d-0d04-0410-961f-82ee72b054a4
* * genemit.c (main): Add tm-constrs.h to included headers.dje2006-03-291-0/+158
* genoutput.c (output_prologue): Add tm-constrs.h to included headers. * genpeep.c (main): Add tm-constrs.h to included headers. * genpreds.c (write_satisfies_constraint_fns): Rename to ... (write_tm_constrs_h): this and write complete file. (write_tm_preds_h): Do not emit satisfies_constraint fns. (write_insn_preds_c): Add tm-constrs.h to included headers. (gen_constrs): New variable. (parse_option): Parse "-c". (main): Invoke write_tm_constrs_h. * genrecog.c (write_header): Add tm-constrs.h to included headers. * Makefile.in (STAGECOPYSTUFF): Add tm-constrs.h. (object_out_file): Add tm-constrs.h dependency. (insn-emit.o): Same. (insn-output.o): Same. (insn-peep.o): Same. (insn-preds.o): Same. (insn-recog.o): Same. (tm-constsr.h): New target. (s-constrs-h): New target. * config/rs6000/constraints.md: New file. * config/rs6000/rs6000.c: Include tm-constrs.h. (num_insn_constant_wide): Convert to satisfies_constraint. (rs6000_rtx_costs): Convert to satisfies_constraint. * config/rs6000/rs6000.h (REG_CLASS_FROM_LETTER): Delete. (CONST_OK_FOR_LETTER_P): Delete. (CONST_DOUBLE_OK_FOR_LETTER_P): Delete. (EXTRA_CONSTRAINT): Delete. (EXTRA_MEMORY_CONSTRAINT): Delete. (EXTRA_ADDRESS_CONSTRAINT): Delete. * config/rs6000/predicates.md: Convert to satisfies_constraint. * config/rs6000/rs6000.md: Include constraints.md. Convert to satisfies_constraint. * config/i386/i386.c: Include tm-constrs.h. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@112508 138bc75d-0d04-0410-961f-82ee72b054a4
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