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* gcc/kyukhin2014-08-111-2/+5
| | | | | | | | | | | | | | | | | | | | | | | * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VL_SET): Define. (OPTION_MASK_ISA_AVX512F_UNSET): Update. (ix86_handle_option): Handle OPT_mavx512vl. * config/i386/cpuid.h (bit_AVX512VL): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512vl, set -mavx512vl accordingly. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_AVX512VL. * config/i386/i386.c (ix86_target_string): Handle -mavx512vl. (ix86_option_override_internal): Define PTA_AVX512VL, handle PTA_AVX512VL and OPTION_MASK_ISA_AVX512VL. (ix86_valid_target_attribute_inner_p): Handle OPT_mavx512vl. * config/i386/i386.h (TARGET_AVX512VL): Define. (TARGET_AVX512VL_P(x)): Ditto. * config/i386/i386.opt: Add mavx512vl. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213813 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/kyukhin2014-08-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BW_SET) : Define. (OPTION_MASK_ISA_AVX512BW_UNSET): Ditto. (OPTION_MASK_ISA_AVX512VL_UNSET) : Ditto. (ix86_handle_option): Handle OPT_mavx512bw. * config/i386/cpuid.h (bit_AVX512BW): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512bw, set -mavx512bw accordingly. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_AVX512BW. * config/i386/i386.c (ix86_target_string): Handle -mavx512bw. (ix86_option_override_internal): Define PTA_AVX512BW, handle PTA_AVX512BW and OPTION_MASK_ISA_AVX512BW. (ix86_valid_target_attribute_inner_p): Handle OPT_mavx512bw. * config/i386/i386.h (TARGET_AVX512BW): Define. (TARGET_AVX512BW_P(x)): Ditto. * config/i386/i386.opt: Add mavx512bw. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213811 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/kyukhin2014-08-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512DQ_SET): Define. (OPTION_MASK_ISA_AVX512DQ_UNSET): Ditto. (ix86_handle_option): Handle OPT_mavx512dq. * config/i386/cpuid.h (bit_AVX512DQ): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512dq, set -mavx512dq accordingly. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_AVX512DQ. * config/i386/i386.c (ix86_target_string): Handle -mavx512dq. (ix86_option_override_internal): Define PTA_AVX512DQ, handle PTA_AVX512DQ and OPTION_MASK_ISA_AVX512DQ. (ix86_valid_target_attribute_inner_p): Handle OPT_mavx512dq. * config/i386/i386.h (TARGET_AVX512DQ): Define. (TARGET_AVX512DQ_P(x)): Ditto. * config/i386/i386.opt: Add mavx512dq. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213757 138bc75d-0d04-0410-961f-82ee72b054a4
* Compute extend family info for AMD CPU and update for BTVER2gganesh2014-08-041-2/+3
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213544 138bc75d-0d04-0410-961f-82ee72b054a4
* remove useless unused attributes in i386 codetbsaunde2014-07-241-2/+1
| | | | | | | | | | | | | gcc/ * config/i386/driver-i386.c: Remove names of unused arguments and unnecessary unused attributes. * config/i386/host-mingw32.c: Likewise. * config/i386/i386.c: Likewise. * config/i386/winnt-stubs.c: Likewise. * config/i386/winnt.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@212968 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/61570jakub2014-06-241-0/+5
| | | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): For unknown model family 6 CPU with has_longmode never use a CPU without 64-bit support. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211945 138bc75d-0d04-0410-961f-82ee72b054a4
* Revert the last change on driver-i386.chjl2014-06-241-37/+16
| | | | | | | | | PR target/61570 * config/i386/driver-i386.c (host_detect_local_cpu): Revert the last change. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211943 138bc75d-0d04-0410-961f-82ee72b054a4
* Assume x86-64 if a 32-bit processor supports SSE2 and 64-bithjl2014-06-231-16/+37
| | | | | | | | | PR target/61570 * config/i386/driver-i386.c (host_detect_local_cpu): Set arch to x86-64 if a 32-bit processor supports SSE2 and 64-bit. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211901 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/kyukhin2014-05-141-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * common/config/i386/i386-common.c (OPTION_MASK_ISA_CLFLUSHOPT_SET): Define. (OPTION_MASK_ISA_XSAVES_SET): Ditto. (OPTION_MASK_ISA_XSAVEC_SET): Ditto. (OPTION_MASK_ISA_CLFLUSHOPT_UNSET): Ditto. (OPTION_MASK_ISA_XSAVES_UNSET): Ditto. (OPTION_MASK_ISA_XSAVEC_UNSET): Ditto. (ix86_handle_option): Handle OPT_mxsavec, OPT_mxsaves, OPT_mclflushopt. * config.gcc (i[34567]86-*-*): Add clflushoptintrin.h, xsavecintrin.h, xsavesintrin.h. (x86_64-*-*): Ditto. * config/i386/clflushoptintrin.h: New. * config/i386/xsavecintrin.h: Ditto. * config/i386/xsavesintrin.h: Ditto. * config/i386/cpuid.h (bit_CLFLUSHOPT): Define. (bit_XSAVES): Ditto. (bit_XSAVES): Ditto. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -mclflushopt, -mxsavec, -mxsaves, -mno-xsaves, -mno-xsavec, -mno-clflushopt. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_CLFLUSHOPT, OPTION_MASK_ISA_XSAVEC, OPTION_MASK_ISA_XSAVES. * config/i386/i386.c (ix86_target_string): Handle -mclflushopt, -mxsavec, -mxsaves. (PTA_CLFLUSHOPT) Define. (PTA_XSAVEC): Ditto. (PTA_XSAVES): Ditto. (ix86_option_override_internal): Handle new options. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_builtins): Add IX86_BUILTIN_XSAVEC, IX86_BUILTIN_XSAVEC64, IX86_BUILTIN_XSAVES, IX86_BUILTIN_XRSTORS, IX86_BUILTIN_XSAVES64, IX86_BUILTIN_XRSTORS64, IX86_BUILTIN_CLFLUSHOPT. (bdesc_special_args): Add __builtin_ia32_xsaves, __builtin_ia32_xrstors, __builtin_ia32_xsavec, __builtin_ia32_xsaves64, __builtin_ia32_xrstors64, __builtin_ia32_xsavec64. (ix86_init_mmx_sse_builtins): Add __builtin_ia32_clflushopt. (ix86_expand_builtin): Handle new builtins. * config/i386/i386.h (TARGET_CLFLUSHOPT) Define. (TARGET_CLFLUSHOPT_P): Ditto. (TARGET_XSAVEC): Ditto. (TARGET_XSAVEC_P): Ditto. (TARGET_XSAVES): Ditto. (TARGET_XSAVES_P): Ditto. * config/i386/i386.md (ANY_XSAVE): Add UNSPECV_XSAVEC, UNSPECV_XSAVES. (ANY_XSAVE64)" Add UNSPECV_XSAVEC64, UNSPECV_XSAVES64. (attr xsave): Add xsavec, xsavec64, xsaves, xsaves64. (ANY_XRSTOR): New. (ANY_XRSTOR64): Ditto. (xrstor): Ditto. (xrstor): Change into <xrstor>. (xrstor_rex64): Change into <xrstor>_rex64. (xrstor64): Change into <xrstor>64 (clflushopt): New. * config/i386/i386.opt (mclflushopt): New. (mxsavec): Ditto. (mxsaves): Ditto. * config/i386/x86intrin.h: Add clflushoptintrin.h, xsavesintrin.h, xsavecintrin.h. * doc/invoke.texi: Document new options. gcc/testsuite/ * gcc.target/i386/clflushopt-1.c: New. * gcc.target/i386/xsavec-1.c: Ditto. * gcc.target/i386/xsavec64-1.c: Ditto. * gcc.target/i386/xsaves-1.c: Ditto. * gcc.target/i386/xsaves64-1.c: Ditto. * gcc.target/i386/sse-12.c: Test new options. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210421 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/kyukhin2014-02-251-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * common/config/i386/i386-common.c (OPTION_MASK_ISA_PREFETCHWT1_SET), (OPTION_MASK_ISA_PREFETCHWT1_UNSET): New. (ix86_handle_option): Handle OPT_mprefetchwt1. * config/i386/cpuid.h (bit_PREFETCHWT1): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect PREFETCHWT1 CPUID. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_PREFETCHWT1. * config/i386/i386.c (ix86_target_string): Handle mprefetchwt1. (PTA_PREFETCHWT1): New. (ix86_option_override_internal): Handle PTA_PREFETCHWT1. (ix86_valid_target_attribute_inner_p): Handle OPT_mprefetchwt1. * config/i386/i386.h (TARGET_PREFETCHWT1), (TARGET_PREFETCHWT1_P): New. * config/i386/i386.md (prefetch): Check TARGET_PREFETCHWT1 (*prefetch_avx512pf_<mode>_: Change into ... (*prefetch_prefetchwt1_<mode>: This. * config/i386/i386.opt (mprefetchwt1): New. * config/i386/xmmintrin.h (_mm_hint): Add _MM_HINT_ET1. (_mm_prefetch): Handle intent to write. * doc/invoke.texi (mprefetchwt1), (mno-prefetchwt1): Doccument. gcc/testsuite/ * gcc.target/i386/avx-1.c: Update __builtin_prefetch. * gcc.target/i386/prefetchwt1-1.c: New. * g++.dg/other/i386-2.C: Add new option. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Update __builtin_prefetch, add new option. * gcc.target/i386/sse-22.c: Add new option. * gcc.target/i386/sse-23.c: Update __builtin_prefetch, add new option. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208115 138bc75d-0d04-0410-961f-82ee72b054a4
* PR driver/60233jakub2014-02-181-22/+23
| | | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): If YMM state is not saved by the OS, also clear has_f16c. Move CPUID 0x80000001 handling before YMM state saving checking. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207833 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years in gcc/rsandifo2014-01-021-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206289 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/kyukhin2013-12-311-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * common/config/i386/i386-common.c (OPTION_MASK_ISA_SHA_SET): New. (OPTION_MASK_ISA_SHA_UNSET): Ditto. (ix86_handle_option): Handle OPT_msha. * config.gcc (extra_headers): Add shaintrin.h. * config/i386/cpuid.h (bit_SHA): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect SHA instructions. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_SHA. * config/i386/i386.c (ix86_target_string): Add -msha. (ix86_option_override_internal): Add PTA_SHA. (ix86_valid_target_attribute_inner_p): Handle OPT_msha. (enum ix86_builtins): Add IX86_BUILTIN_SHA1MSG1, IX86_BUILTIN_SHA1MSG2, IX86_BUILTIN_SHA1NEXTE, IX86_BUILTIN_SHA1RNDS4, IX86_BUILTIN_SHA256MSG1, IX86_BUILTIN_SHA256MSG2, IX86_BUILTIN_SHA256RNDS2. (bdesc_args): Add BUILTINS defined above. (ix86_init_mmx_sse_builtins): Add __builtin_ia32_sha1msg1, __builtin_ia32_sha1msg2, __builtin_ia32_sha1nexte, __builtin_ia32_sha1rnds4, __builtin_ia32_sha256msg1, __builtin_ia32_sha256msg2, __builtin_ia32_sha256rnds2. (ix86_expand_args_builtin): Handle V4SI_FTYPE_V4SI_V4SI_V4SI, add warning for CODE_FOR_sha1rnds4. * config/i386/i386.h (TARGET_SHA): New. (TARGET_SHA_P): Ditto. * config/i386/i386.opt (-msha): Document it. * config/i386/immintrin.h: Add shaintrin.h. * config/i386/shaintrin.h: New. * config/i386/sse.md (unspec): Add UNSPEC_SHA1MSG1, UNSPEC_SHA1MSG2, UNSPEC_SHA1NEXTE, UNSPEC_SHA1RNDS4, UNSPEC_SHA256MSG1, UNSPEC_SHA256MSG2, UNSPEC_SHA256RNDS2. (sha1msg1): New. (sha1msg2): Ditto. (sha1nexte): Ditto. (sha1rnds4): Ditto. (sha256msg1): Ditto. (sha256msg2): Ditto. (sha256rnds2): Ditto. * doc/invoke.texi: Add -msha. testsuite/ * gcc.target/i386/avx-1.c: Add define for __builtin_ia32_sha1rnds4. * gcc.target/i386/i386.exp (check_effective_target_sha): New. * gcc.target/i386/sha-check.h: New file. * gcc.target/i386/sha1msg1-1.c: Ditto. * gcc.target/i386/sha1msg1-2.c: Ditto. * gcc.target/i386/sha1msg2-1.c: Ditto. * gcc.target/i386/sha1msg2-2.c: Ditto. * gcc.target/i386/sha1nexte-1: Ditto. * gcc.target/i386/sha1nexte-2: Ditto. * gcc.target/i386/sha1rnds4-1.c: Ditto. * gcc.target/i386/sha1rnds4-2.c: Ditto. * gcc.target/i386/sha256msg1-1.c: Ditto. * gcc.target/i386/sha256msg1-2.c: Ditto. * gcc.target/i386/sha256msg2-1.c: Ditto. * gcc.target/i386/sha256msg2-2.c: Ditto. * gcc.target/i386/sha256rnds2-1.c: Ditto. * gcc.target/i386/sha256rnds2-2.c: Ditto. * gcc.target/i386/sse-13.c: Add __builtin_ia32_sha1rnds4. * gcc.target/i386/sse-14.c: Add _mm_sha1rnds4_epu32. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Add __builtin_ia32_sha1rnds4. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206263 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/driver-i386.c (decode_caches_intel): Add missing entries.uros2013-12-261-0/+18
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206203 138bc75d-0d04-0410-961f-82ee72b054a4
* Use proper Intel processor names for -march=/-mtune=hjl2013-12-231-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/i386/core2.md: Replace corei7 with nehalem. * config/i386/driver-i386.c (host_detect_local_cpu): Use nehalem, westmere, sandybridge, ivybridge, haswell, bonnell, silvermont for cpu names. * config/i386/i386-c.c (ix86_target_macros_internal): Replace PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM, PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE, PROCESSOR_BONNELL, PROCESSOR_SILVERMONT. Define __nehalem/__nehalem__, __sandybridge/__sandybridge__, __haswell/__haswell__, __tune_nehalem__, __tune_sandybridge__, __tune_haswell__, __bonnell/__bonnell__, __silvermont/__silvermont__, __tune_bonnell__, __tune_silvermont__. * config/i386/i386.c (m_COREI7): Renamed to ... (m_NEHALEM): This. (m_COREI7_AVX): Renamed to ... (m_SANDYBRIDGE): This. (m_ATOM): Renamed to ... (m_BONNELL): This. (m_SLM): Renamed to ... (m_SILVERMONT): This. (m_CORE_ALL): Updated. (cpu_names): Add "nehalem", "westmere", "sandybridge", "ivybridge", "haswell", "broadwell", "bonnell", "silvermont". (PTA_CORE2): New. (PTA_NEHALEM): Likewise. (PTA_WESTMERE): Likewise. (PTA_SANDYBRIDGE): Likewise. (PTA_IVYBRIDGE): Likewise. (PTA_HASWELL): Likewise. (PTA_BROADWELL): Likewise. (PTA_BONNELL): Likewise. (PTA_SILVERMONT): Likewise. (ix86_option_override_internal): Use new PTA_XXX. Add nehalem, westmere, sandybridge, ivybridge, haswell, bonnell, silvermont. (ix86_lea_outperforms): Updated. (ix86_issue_rate): Likewise. (ix86_adjust_cost): Likewise. (ia32_multipass_dfa_lookahead): Likewise. (do_reorder_for_imul): Likewise. (swap_top_of_ready_list): Likewise. (ix86_sched_reorder): Likewise. (ix86_sched_init_global): Likewise. (get_builtin_code_for_version): Likewise. (processor_model): Replace M_INTEL_ATOM, M_INTEL_SLM with M_INTEL_BONNELL, M_INTEL_SILVERMONT. (arch_names_table): Updated. * config/i386/i386.h (TARGET_COREI7): Removed. (TARGET_COREI7_AVX): Likewise. (TARGET_ATOM): Likewise. (TARGET_SLM): Likewise. (TARGET_NEHALEM): New. (TARGET_SANDYBRIDGE): Likewise. (TARGET_BONNELL): Likewise. (TARGET_SILVERMONT): Likewise. (target_cpu_default): Add TARGET_CPU_DEFAULT_core_avx2, TARGET_CPU_DEFAULT_nehalem, TARGET_CPU_DEFAULT_westmere, TARGET_CPU_DEFAULT_sandybridge, TARGET_CPU_DEFAULT_ivybridge, TARGET_CPU_DEFAULT_broadwell, TARGET_CPU_DEFAULT_bonnell, TARGET_CPU_DEFAULT_silvermont. Move TARGET_CPU_DEFAULT_haswell before TARGET_CPU_DEFAULT_broadwell. (processor_type): Replace PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM, PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE, PROCESSOR_BONNELL, PROCESSOR_SILVERMONT. * config/i386/i386.md (cpu): Replace corei7 with nehalem. * config/i386/x86-tune.def: Updated. * doc/invoke.texi: Replace corei7, corei7-avx, core-avx-i, core-avx2, atom, slm with nehalem, sandybridge, ivybridge, haswell, bonnel, silvermont. Add westmere. libgcc/ * config/i386/cpuinfo.c (processor_subtypes): Replace INTEL_ATOM, INTEL_SLM with INTEL_BONNELL, INTEL_SILVERMONT. (get_intel_cpu): Updated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206178 138bc75d-0d04-0410-961f-82ee72b054a4
* * config.gcc: Support march=broadwell.kyukhin2013-12-201-1/+3
| | | | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Detect Broadwell. * config/i386/i386.c (ix86_option_override_internal): Add broadwell. * doc/invoke.texi: Document march=broadwell. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206144 138bc75d-0d04-0410-961f-82ee72b054a4
* Enable AES, PCLMUL and RDRND for Silvermonthjl2013-11-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | gcc/ 2013-11-22 Yuri Rumyantsev <ysrumyan@gmail.com> * config/i386/i386.c(processor_alias_table): Enable PTA_AES, PTA_PCLMUL and PTA_RDRND for Silvermont. * config/i386/driver-i386.c (host_detect_local_cpu): Set up cpu for Silvermont. * doc/invoke.texi: Mention AES, PCLMUL and RDRND for Silvermont. libgcc/ 2013-11-22 Yuri Rumyantsev <ysrumyan@gmail.com> * config/i386/cpuinfo.c (get_intel_cpu): Add Silvermont cases. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205275 138bc75d-0d04-0410-961f-82ee72b054a4
* AMD bdver4 enablementgganesh2013-11-181-0/+5
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204939 138bc75d-0d04-0410-961f-82ee72b054a4
* * i386.h (TARGET_GENERIC32, TARGET_GENERIC64): Remove.hubicka2013-09-191-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | (TARGET_GENERIC): Use PROCESOR_GENERIC (enum processor_type): Unify generic32 and 64. * i386.md (cpu): Likewise. * x86-tune.def (use_leave): Enable for generic32. (avoid_vector_decode, slow_imul_imm32_mem, slow_imul_imm8): Likewise. * athlon.md: Change generic64 to generic in all occurences. * i386-c.c (ix86_target_macros_internal): Unify generic64 and 32. (ix86_target_macros_internal): Likewise. * driver-i386.c (host_detect_local_cpu): Likewise. * i386.c (generic64_memcpy, generic64_memset, generic64_cost): Rename to .. (generic_memcpy, generic_memset, generic_cost): This one. (generic32_memcpy, generic32_memset, generic32_cost): Remove. (m_GENERIC32, m_GENERIC64): Remove. (m_GENERIC): Turn into one flag. (processor_target): Unify generic tunnings. (ix86_option_override_internal): Replace generic32/64 by generic. (ix86_issue_rate): Likewise. (ix86_adjust_cost): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202741 138bc75d-0d04-0410-961f-82ee72b054a4
* Update Haswell processor detectionhjl2013-08-271-0/+2
| | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Update Haswell processor detection. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202028 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/57927uros2013-08-271-10/+18
| | | | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Add detection of Ivy Bridge and Haswell processors. Assume core-avx2 for unknown AVX2 capable processors. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202026 138bc75d-0d04-0410-961f-82ee72b054a4
* * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512F_SET): New.kyukhin2013-08-221-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (OPTION_MASK_ISA_AVX512CD_SET): Ditto. (OPTION_MASK_ISA_AVX512PF_SET): Ditto. (OPTION_MASK_ISA_AVX512ER_SET): Ditto. (OPTION_MASK_ISA_AVX2_UNSET): Update. (OPTION_MASK_ISA_AVX512F_UNSET): New. (OPTION_MASK_ISA_AVX512CD_UNSET): Ditto. (OPTION_MASK_ISA_AVX512PF_UNSET): Ditto. (OPTION_MASK_ISA_AVX512ER_UNSET): Ditto. (ix86_handle_option): Handle OPT_mavx512f, OPT_mavx512cd, OPT_mavx512pf, OPT_mavx512er cases. * config/i386/constraints.md (v): New constraint. (Yi, Yj): Replace SSE_REGS with ALL_SSE_REGS. * config/i386/cpuid.h (bit_AVX512F, bit_AVX512PF, bit_AVX512ER) (bit_AVX512CD): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect AVX512F, AVX512ER, AVX512PF, AVX512CD features. * config/i386/i386-c.c (ix86_target_macros_internal): Conditionally define __AVX512F__, __AVX512ER__, __AVX512CD__, __AVX512PF__. * config/i386/i386-modes.def (VECTOR_MODES (INT, 128)) (VECTOR_MODES (FLOAT, 128), INT_MODE (XI, 64)): New modes. * config/i386/i386.c (regclass_map, dbx_register_map) (dbx64_register_map, svr4_dbx_register_map): Add new SSE registers. (gate_insert_vzeroupper): Disable vzeroupper for TARGET_AVX512F. (ix86_target_string): Define -mavx512f, -mavx512er, -mavx512cd, -mavx512pf options. (ix86_option_override_internal): Define PTA_AVX512F, PTA_AVX512ER, PTA_AVX512PF, PTA_AVX512CD. Handle -mavx512f, -mavx512er, -mavx512cd, -mavx512pf options. Fix formatting. (ix86_conditional_register_usage): Squash EXT_REX_SSE_REGs for 32-bit targets. Squash EVEX_SSE_REGS if AVX512F is disabled. (ix86_valid_target_attribute_inner_p): Handle -mavx512f, -mavx512er, -mavx512cd, -mavx512pf options. (standard_sse_constant_opcode): Add vpternlogd for 512-bit modes. (print_reg, ix86_print_operand): Handle 'g' to output 512-bit operands. (ix86_preferred_output_reload_class): Replace SSE_REGS with ALL_SSE_REGS. (ix86_hard_regno_mode_ok): Support 512-bit registers. (ix86_set_reg_reg_cost): Ditto. (x86_order_regs_for_local_alloc): Ditto. (MAX_VECT_LEN): Extend to 64-byte. (ix86_spill_class): Replace SSE_REGS with ALL_SSE_REGS. * config/i386/i386.h (TARGET_AVX512F, TARGET_AVX512PF) (TARGET_AVX512ER, TARGET_AVX512CD): New. (BIGGEST_ALIGNMENT): Extend to 512-bits. (FIRST_PSEUDO_REGISTER, FIXED_REGISTERS): Add new registers. (CALL_USED_REGISTERS, REG_ALLOC_ORDER): Likewise. (VALID_AVX512F_SCALAR_MODE, VALID_AVX512F_REG_MODE): New. (SSE_REG_MODE_P): Support new modes. (FIRST_MMX_REG, FIRST_REX_INT_REG, FIRST_REX_SSE_REG): Add comments. (FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG): New. (reg_class, REG_CLASS_NAMES): Add EVEX_SSE_REGS, ALL_SSE_REGS. (SSE_CLASS_P, MAYBE_SSE_CLASS_P): Replace SSE_REGS with ALL_SSE_REGS. (REG_CLASS_CONTENTS): Add new registers. (SSE_REGNO_P, SSE_REGNO, HARD_REGNO_RENAME_OK): Support new registers. (EXT_REX_SSE_REGNO_P): New. (HI_REGISTER_NAMES): Add new registers. * config/i386/i386.md: Define constants for new registers. (mode): Add new 512-bit modes. (prefix): Support evex prefix. (isa): Support avx512f, noavx512f, fma_avx512f. (ssemodesuffix): Add new 512-bit modes. (movxi): New. (*movxi_internal_avx512f): Ditto. (*movdi_internal): Replace constraint "x" with the new constraint "v". Support MODE_XI. (*movsi_internal): Likewise. (*movdf_internal): Likewise. (*movsf_internal): Likewise. (*fop_<mode>_comm_sse): Replace constraint "x" with new constraint "v". (<code><mode>3): Likewise. * config/i386/i386.opt (mavx512f, mavx512pf, mavx512er, mavx512cd): New. * config/i386/mmx.md (*mov<mode>_internal): Replace constraint "x" with the new constraint "v". * config/i386/sse.md (*mov<mode>_internal): Support new registers and modes. (<sse>_loadu<ssemodesuffix><avxsizesuffix>): Replace constraint "x" with the new constraint "v". (<sse2>_loaddqu<avxsizesuffix>): Likewise. (<sse2>_storedqu<avxsizesuffix>): Likewise. (*<plusminus_insn><mode>3): Likewise. (<sse>_vm<plusminus_insn><mode>3): Likewise. (*mul<mode>3): Likewise. (<sse>_vmmul<mode>3): Likewise. (<sse>_div<mode>3): Likewise. (<sse>_vmdiv<mode>3): Likewise. (<sse>_sqrt<mode>2): Likewise. (<sse>_vmsqrt<mode>2): Likewise. (*<code><mode>3_finite): Likewise. (*<code><mode>3) <smaxmin>: Likewise. (<sse>_vm<code><mode>3): Likewise. (*<code><mode>3) <any_logic>: Likewise. (*fma_fmadd_<mode>): Likewise. (*fma_fmsub_<mode>): Likewise. (*fma_fnmadd_<mode>): Likewise. (*fma_fnmsub_<mode>): Likewise. (*fma_fmaddsub_<mode>): Likewise. (*fma_fmsubadd_<mode>): Likewise. (*fmai_fmadd_<mode>): Likewise. (*fmai_fmsub_<mode>): Likewise. (*fmai_fnmadd_<mode>): Likewise. (*fmai_fnmsub_<mode>): Likewise. (sse_cvtsi2ss): Likewise. (sse_cvtsi2ssq): Likewise. (sse_cvtss2si): Likewise. (sse_cvtss2si_2): Likewise. (sse_cvtss2siq): Likewise. (sse_cvtss2siq_2): Likewise. (sse_cvttss2si): Likewise. (sse_cvtss2siq_2): Likewise. (float<sseintvecmodelower><mode>2): Likewise. (sse2_cvtsd2si_2): Likewise. (sse2_cvtsd2siq_2): Likewise. (*<plusminus_insn><mode>3): Likewise. (*<sse2_avx2>_<plusminus_insn><mode>3): Likewise. (*<sse4_1_avx2>_mul<mode>3): Likewise. (ashr<mode>3): Likewise. (<shift_insn><mode>3): Likewise. (avx2_<code><mode>3): Likewise. (*avx2_<code><mode>3): Likewise. (*andnot<mode>3): Likewise. (*<code><mode>3) <any_logic>: Likewise. (abs<mode>2): Likewise. (avx2_permvar<mode>): Likewise. (avx2_perm<mode>_1): Likewise. (*avx_vpermilp<mode>): Likewise. (avx_vpermilvar<mode>3): Likewise. (avx2_ashrv<mode>): Likewise. (avx2_<shift_insn>v<mode>): Likewise. * doc/invoke.texi: Document -mavx512f, -mavx512pf, -mavx512er, -mavx512cd. * doc/rtl.texi: Document XImode. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@201915 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/driver-i386.c (host_detect_local_cpu): Do not checkuros2013-07-071-2/+1
| | | | | | | | signature_TM2_ebx, it interferes with signature_INTEL_ebx. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@200744 138bc75d-0d04-0410-961f-82ee72b054a4
* Silvermont (SLM) architecture pipeline model, tuning andkyukhin2013-05-301-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | insn selection. * config.gcc: Add slm config options and target. * config/i386/slm.md: New. * config/i386/driver-i386.c (host_detect_local_cpu): Check movbe. * gcc/config/i386/i386-c.c (ix86_target_macros_internal): New case PROCESSOR_SLM. (ix86_target_macros_internal): Likewise. * gcc/config/i386/i386.c (slm_cost): New cost. (m_SLM): New macro flag. (initial_ix86_tune_features): Set m_SLM. (x86_accumulate_outgoing_args): Likewise. (x86_arch_always_fancy_math_387): Likewise. (processor_target_table): Add slm cost. (cpu_names): Add slm cpu name. (x86_option_override_internal): Set SLM ISA. (ix86_issue_rate): New case PROCESSOR_SLM. (ia32_multipass_dfa_lookahead): Likewise. (fold_builtin_cpu): Add slm. * config/i386/i386.h (TARGET_SLM): New target macro. (target_cpu_default): Add TARGET_CPU_DEFAULT_slm. (processor_type): Add PROCESSOR_SLM. * config/i386/i386.md (cpu): Add new value "slm". (slm.md): Include slm.md. * libgcc/config/i386/cpuinfo.c (INTEL_SLM): New enum value. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@199444 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/driver-i386.c (host_detect_local_cpu): Pass mmx, 3dnow,uros2013-05-171-2/+10
| | | | | | | | sse, sse2, sse3, ssse3 and sse4a flags to options. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@199034 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/i386/driver-i386.c (host_detect_local_cpu): Determineuros2013-05-161-10/+18
| | | | | | | | | cache parameters using detect_caches_amd also for CYRIX, NSC and TM2 signatures. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198989 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/45359uros2013-05-161-1/+28
| | | | | | | | | | | PR target/46396 * config/i386/driver-i386.c (host_detect_local_cpu): Detect VIA/Centaur processors and determine their cache parameters using detect_caches_amd. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198987 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years in gcc/rsandifo2013-01-101-2/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195098 138bc75d-0d04-0410-961f-82ee72b054a4
* AMD bdver3 enablementgganesh2012-11-161-0/+5
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@193548 138bc75d-0d04-0410-961f-82ee72b054a4
* ChangeLog/kyukhin2012-10-261-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA_FXSR_SET): New. (OPTION_MASK_ISA_XSAVE_SET): Likewise. (OPTION_MASK_ISA_XSAVEOPT_SET): Likewise. (ix86_handle_option): Handle mfxsr, mxsave, mxsaveopt options. * gcc/config.gcc (i[34567]86-*-*): Add fxsrintrin.h, xsaveintrin.h, xsaveoptintrin.h. (x86_64-*-*): Likewise. * config/i386/fxsrintrin.h: New header. * config/i386/xsaveintrin.h: Likewise. * config/i386/xsaveoptintrin.h: Likewise. * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect FXSR/XSAVE/XSAVEOPT support. * gcc/config/i386/i386-builtin-types.def (VOID_FTYPE_PVOID_INT64): New function type. * gcc/config/i386/i386-c.c: Define __FXSR__, __XSAVE__ and __XSAVEOPT__ if needed. * gcc/config/i386/i386.c (ix86_target_string): Define -mfxsr, -mxsave and -mxsaveopt options. (PTA_FXSR): New. (PTA_XSAVE): Likewise. (PTA_XSAVEOPT): Likewise. (ix86_option_override_internal): Handle new option. (processor_alias_table): Added PTA_FXSR, PTA_XSAVE, PTA_XSAVEOPT. (ix86_valid_target_attribute_inner_p): Add OPT_mfxsr, OPT_mxsave, OPT_mxsaveopt. (ix86_builtins): Add IX86_BUILTIN_FXSAVE, IX86_BUILTIN_FXRSTOR, IX86_BUILTIN_FXSAVE64, IX86_BUILTIN_XSAVE, IX86_BUILTIN_XSAVE64, IX86_BUILTIN_XRSTOR, IX86_BUILTIN_XRSTOR64, IX86_BUILTIN_XSAVEOPT, IX86_BUILTIN_XSAVEOPT64. (ix86_expand_builtin): Handle these built-ins. * gcc/config/i386/i386.h (TARGET_FXSR): New. (TARGET_XSAVE): Likewise. (TARGET_XSAVEOPT): Likewise. * gcc/config/i386/i386.md (ANY_XSAVE): New int iterator. (ANY_XSAVE64): Likewise. (xsave): New int attribute. (fxsave): New instruction. (fxsave64): Likewise. (fxrstor): Likewise. (fxrstor64): Likewise. (<xsave>): Likewise. (<xsave>_rex64): Likewise. (xrstor): Likewise. (xrstor_rex64): Likewise. (xrstor64): Likewise. * gcc/config/i386/i386.opt (mfxsr): New. (mxsave): Likewise. (mxsaveopt): Likewise. * gcc/config/i386/x86intrin.h: Include xsaveintrin.h, fxsrintrin.h, xsaveoptintrin.h. testsuite/ChangeLog * gcc.target/i386/fxsave-1.c: New. * gcc.target/i386/fxsave64-1.c: Ditto. * gcc.target/i386/fxrstor-1.c: Ditto. * gcc.target/i386/fxrstor64-1.c: Ditto. * gcc.target/i386/xsave-1.c: Ditto. * gcc.target/i386/xsave64-1.c: Ditto. * gcc.target/i386/xrstor-1.c: Ditto. * gcc.target/i386/xrstor64-1.c: Ditto. * gcc.target/i386/xsaveopt-1.c: Ditto. * gcc.target/i386/xsaveopt64-1.c: Ditto. * gcc.target/i386/sse-12.c: Add -mfxsr, -mxsaveopt. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@192840 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix SSE and YMM state support check logic for -march=nativehjl2012-10-031-1/+2
| | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Fix logic in SSE and YMM state support check for -march=native. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@192044 138bc75d-0d04-0410-961f-82ee72b054a4
* Check SSE and YMM state support for -march=nativehjl2012-10-021-0/+22
| | | | | | | | | | | | | | | 2012-10-02 H.J. Lu <hongjiu.lu@intel.com> PR target/54741 * config/i386/driver-i386.c (XCR_XFEATURE_ENABLED_MASK): New. (XSTATE_FP): Likewise. (XSTATE_SSE): Likewise. (XSTATE_YMM): Likewise. (host_detect_local_cpu): Disable AVX, AVX2, FMA, FMA4 and XOP if SSE and YMM states aren't supported. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@191998 138bc75d-0d04-0410-961f-82ee72b054a4
* 2012-09-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>uros2012-09-121-2/+0
| | | | | | | | | | | | | | | | * config/i386/i386.md : Comments on fma4 instruction selection reflect requirement on register pressure based cost model. * config/i386/driver-i386.c (host_detect_local_cpu): fma4 flag is set-reset as informed by the cpuid flag. * config/i386/i386.c (processor_alias_table): fma4 flag is enabled for bdver2. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@191226 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/drepper2012-09-091-17/+6
| | | | | | | | | | | | | | | | | | * config/i386/cpuid.h: Define signature_*_e[bcd]x macros for matching results of level 0 calls to __cpuid to processor manufacturers. * config/i386/driver-i386.c (vendor_signatures): Removed. (processor_signatures): Removed. (host_detect_local_cpu): Replace uses of now-removed SIG_* constants with the new signature_*_ebx constants. libstdc++-v3/ * src/c++11/random.cc (random_device::_M_init): Use new macro signature_INTEL_ebx to check for Intel processors. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@191109 138bc75d-0d04-0410-961f-82ee72b054a4
* PR driver/54210jakub2012-08-131-2/+3
| | | | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Test bit_PRFCHW bit of CPUID 0x80000001 %ecx instead of CPUID 7 %ecx. * config/i386/cpuid.h (bits_PRFCHW): Move definition to CPUID 0x80000001 %ecx flags. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@190345 138bc75d-0d04-0410-961f-82ee72b054a4
* ChangeLog:kyukhin2012-08-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2012-08-08 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_ADX_SET): New. (OPTION_MASK_ISA_ADX_UNSET): Likewise. (ix86_handle_option): Handle madx option. * config.gcc (i[34567]86-*-*): Add adxintrin.h. (x86_64-*-*): Likewise. * config/i386/adxintrin.h: New header. * config/i386/driver-i386.c (host_detect_local_cpu): Detect ADCX/ADOX support. * config/i386/i386-builtin-types.def (UCHAR_FTYPE_UCHAR_UINT_UINT_PUNSIGNED): New function type. (UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG): Likewise. * config/i386/i386-c.c: Define __ADX__ if needed. * config/i386/i386.c (ix86_target_string): Define -madx option. (PTA_ADX): New. (ix86_option_override_internal): Handle new option. (ix86_valid_target_attribute_inner_p): Add OPT_madx. (ix86_builtins): Add IX86_BUILTIN_ADDCARRYX32, IX86_BUILTIN_ADDCARRYX64. (ix86_init_mmx_sse_builtins): Define corresponding built-ins. (ix86_expand_builtin): Handle these built-ins. (ix86_expand_args_builtin): Handle new function types. * config/i386/i386.h (TARGET_ADX): New. * config/i386/i386.md (adcx<mode>3): New define_insn. * config/i386/i386.opt (madx): New. * config/i386/x86intrin.h: Include adxintrin.h. testsuite/ChangeLog: * gcc.target/i386/adx-addcarryx32-1.c: New. * gcc.target/i386/adx-addcarryx32-2.c: New. * gcc.target/i386/adx-addcarryx64-1.c: New. * gcc.target/i386/adx-addcarryx64-2.c: New. * gcc.target/i386/adx-check.h: New. * gcc.target/i386/i386.exp (check_effective_target_adx): New. * gcc.target/i386/sse-12.c: Add -madx. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@190227 138bc75d-0d04-0410-961f-82ee72b054a4
* /kyukhin2012-07-301-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * common/config/i386/i386-common.c (OPTION_MASK_ISA_RDSEED_SET): New. (OPTION_MASK_ISA_RDSEED_UNSET): Likewise. (ix86_handle_option): Handle mrdseed option. * config.gcc (i[34567]86-*-*): Add rdseedintrin.h. (x86_64-*-*): Likewise. * config/i386/prfchwintrin.h: New header. * config/i386/cpuid.h (bit_RDSEED): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect RDSEED support. * config/i386/i386-c.c: Define __RDSEED__ if needed. * config/i386/i386.c (ix86_target_string): Define -mrdseed option. (PTA_RDSEED): New. (ix86_option_override_internal): Handle new option. (ix86_valid_target_attribute_inner_p): Add OPT_mrdseed. (ix86_builtins): Add enum entries for RDSEED* builtins. (ix86_init_mmx_sse_builtins): Define new builtins. (ix86_expand_builtin): Expand RDSEED* builtins. * config/i386/i386.h (TARGET_RDSEED): New. * config/i386/i386.md (rdseed<mode>_1): New. * config/i386/i386.opt (mrdseed): New. * config/i386/x86intrin.h: Include rdseedintrin.h. testsuite/ * gcc.target/i386/rdseed16-1.c: New. * gcc.target/i386/rdseed32-1.c: Ditto * gcc.target/i386/rdseed64-1.c: Ditto * gcc.target/i386/sse-12.c: Add -mrdseed. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@189973 138bc75d-0d04-0410-961f-82ee72b054a4
* Changelog entry:kyukhin2012-07-251-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2012-07-25 Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_PRFCHW_SET): New. (OPTION_MASK_ISA_PRFCHW_UNSET): Likewise. (ix86_handle_option): Handle mprfchw option. * config.gcc (i[34567]86-*-*): Add prfchwintrin.h. (x86_64-*-*): Likewise. * config/i386/prfchwintrin.h: New header. * config/i386/cpuid.h (bit_PRFCHW): New. (bit_BMI): Formatting fix. (bit_HLE): Likewise. (bit_RTM): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Detect PREFETCHW support. * config/i386/i386-c.c: Define __PRFCHW__ if needed. * config/i386/i386.c (ix86_target_string): Define -mprfchw option. Formatting fixes. (PTA_HLE): Formatting fix. (PTA_PRFCHW): New. (ix86_option_override_internal): Handle new option. (ix86_valid_target_attribute_inner_p): Add OPT_mprfchw. * config/i386/i386.h (TARGET_PRFCHW): New. * config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW. * config/i386/i386.opt (mprfchw): New. * config/i386/mm3dnow.h: Move _m_prefetchw from here to prfchwintrin.h. * config/i386/x86intrin.h: Include prfchwintrin.h. testsuite/Changelog entry: 2012-07-24 Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gcc.target/i386/prefetchw-1.c: New. * gcc.target/i386/sse-12.c: Add -mprfchw. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@189844 138bc75d-0d04-0410-961f-82ee72b054a4
* AMD btver2 enablementvekumar2012-07-251-0/+5
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@189838 138bc75d-0d04-0410-961f-82ee72b054a4
* Add RDRND, F16C and FSGSBASE support to -march=nativehjl2012-05-201-1/+8
| | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Support RDRND, F16C and FSGSBASE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187696 138bc75d-0d04-0410-961f-82ee72b054a4
* Add RTM support to -march=nativehjl2012-05-111-2/+4
| | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Support RTM. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187400 138bc75d-0d04-0410-961f-82ee72b054a4
* With -march=native generate fma3 instruction by default for AMD processors ↵vekumar2012-05-031-0/+2
| | | | | | which support both fma and fma4 git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187077 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/53201kyukhin2012-05-031-1/+1
| | | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Add space to "-mno-hle". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187075 138bc75d-0d04-0410-961f-82ee72b054a4
* ChangeLog entry:kyukhin2012-05-021-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * coretypes (MEMMODEL_MASK): New. * builtins.c (get_memmodel): Add val. Call target.memmodel_check and return new variable. (expand_builtin_atomic_exchange): Mask memmodel values. (expand_builtin_atomic_compare_exchange): Ditto. (expand_builtin_atomic_load): Ditto. (expand_builtin_atomic_store): Ditto. (expand_builtin_atomic_clear): Ditto. * doc/extend.texi: Mention port-dependent memory model flags. * config/i386/cpuid.h (bit_HLE): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect HLE support. * config/i386/i386-protos.h (ix86_generate_hle_prefix): New. * config/i386/i386-c.c (ix86_target_macros_internal): Set HLE defines. (ix86_target_string)<-mhle>: New. (ix86_valid_target_attribute_inner_p)<OPT_mhle>: Ditto. * config/i386/i386.c (ix86_target_string)<OPTION_MASK_ISA_HLE>: New. (ix86_valid_target_attribute_inner_p)<OPT_mhle>: Ditto. (ix86_option_override_internal)<PTA_HLE>: New switch, set it enabled for generic, generic64 and core-avx2. (ix86_print_operand): Generate HLE lock prefixes. (ix86_memmodel_check): New. (TARGET_MEMMODEL_CHECK): Ditto. * config/i386/i386.h (OPTION_ISA_HLE): Ditto. (IX86_HLE_ACQUIRE): Ditto. (IX86_HLE_RELEASE): Ditto. * config/i386/i386.h (ix86_generate_hle_prefix): Ditto. * config/i386/i386.opt (mhle): Ditto. * config/i386/sync.md(atomic_compare_and_swap<mode>): Pass success model to instruction emitter. (atomic_fetch_add<mode>): Ditto. (atomic_exchange<mode>): Ditto. (atomic_add<mode>): Ditto. (atomic_sub<mode>): Ditto. (atomic_<code><mode>): Ditto. (*atomic_compare_and_swap_doubledi_pic): Ditto. (atomic_compare_and_swap_single<mode>): Define and use argument for success model. (atomic_compare_and_swap_double<mode>): Ditto. * configure.ac: Check if assembler support HLE prefixes. * configure: Regenerate. * config.in: Ditto. testsuite/ChangeLog entry: * gcc.target/i386/hle-cmpxchg-acq-1.c: New. * gcc.target/i386/hle-cmpxchg-rel-1.c: Ditto. * gcc.target/i386/hle-add-acq-1.c: Ditto. * gcc.target/i386/hle-add-rel-1.c: Ditto. * gcc.target/i386/hle-and-acq-1.c: Ditto. * gcc.target/i386/hle-and-rel-1.c: Ditto. * gcc.target/i386/hle-or-acq-1.c: Ditto. * gcc.target/i386/hle-or-rel-1.c: Ditto. * gcc.target/i386/hle-sub-acq-1.c: Ditto. * gcc.target/i386/hle-sub-rel-1.c: Ditto. * gcc.target/i386/hle-xadd-acq-1.c: Ditto. * gcc.target/i386/hle-xadd-rel-1.c: Ditto. * gcc.target/i386/hle-xchg-acq-1.c: Ditto. * gcc.target/i386/hle-xchg-rel-1.c: Ditto. * gcc.target/i386/hle-xor-acq-1.c: Ditto. * gcc.target/i386/hle-xor-rel-1.c: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187051 138bc75d-0d04-0410-961f-82ee72b054a4
* 2011-12-19 Quentin Neill <quentin.neill@amd.com>qneill2011-12-191-1/+1
| | | | | | | | | | | | 2011-12-19 Quentin Neill <quentin.neill@amd.com> PR target/48743 * config/i386/driver-i386.c (host_detect_local_cpu): Also check family to distinguish PROCESSOR_ATHLON. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@182489 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/50740uros2011-10-211-6/+9
| | | | | | | | | | | | | | | * config/i386/driver-i386.c (host_detect_local_cpu): Do cpuid 7 only if max_level allows that. testsuite/ChangeLog: PR target/50740 * gcc.target/i386/avx2-check.h (main): Check CPUID level correctly. * gcc.target/i386/bmi2-check.h: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180304 138bc75d-0d04-0410-961f-82ee72b054a4
* Add BMI2 support.hjl2011-08-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ 2011-08-23 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (type): Add imulx, ishiftx and rotatex. (length_immediate): Handle imulx, ishiftx and rotatex. (imm_disp): Ditto. (isa): Add bmi2. (enabled): Handle bmi2. (w): New mode attribute. (*mul<mode><dwi>3): Split from *<u>mul<mode><dwi>3. (*umul<mode><dwi>3): Ditto. Add imulx BMI2 alternative. (*bmi2_umulditi3_1): New insn pattern. (*bmi2_umulsidi3_1): Ditto. (*umul<mode><dwi>3 splitter): New splitter to avoid flags dependency. (*bmi2_ashl<mode>3_1): New insn pattern. (*ashl<mode>3_1): Add ishiftx BMI2 alternative. (*ashl<mode>3_1 splitter): New splitter to avoid flags dependency. (*bmi2_ashlsi3_1_zext): New insn pattern. (*ashlsi3_1_zext): Add ishiftx BMI2 alternative. (*ashlsi3_1_zext splitter): New splitter to avoid flags dependency. (*bmi2_<shiftrt_insn><mode>3_1): New insn pattern. (*<shiftrt_insn><mode>3_1): Add ishiftx BMI2 alternative. (*<shiftrt_insn><mode>3_1 splitter): New splitter to avoid flags dependency. (*bmi2_<shiftrt_insn>si3_1_zext): New insn pattern. (*<shiftrt_insn>si3_1_zext): Add ishiftx BMI2 alternative. (*<shiftrt_insn>si3_1_zext splitter): New splitter to avoid flags dependency. (*bmi2_rorx<mode>3_1): New insn pattern. (*<rotate_insn><mode>3_1): Add rotatex BMI2 alternative. (*rotate<mode>3_1 splitter): New splitter to avoid flags dependency. (*rotatert<mode>3_1 splitter): Ditto. (*bmi2_rorxsi3_1_zext): New insn pattern. (*<rotate_insn>si3_1_zext): Add rotatex BMI2 alternative. (*rotatesi3_1_zext splitter): New splitter to avoid flags dependency. (*rotatertsi3_1_zext splitter): Ditto. 2011-08-23 Kirill Yukhin <kirill.yukhin@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_BMI2_SET): New. (OPTION_MASK_ISA_BMI2_UNSET): Likewise. (ix86_handle_option): Handle OPT_mbmi2 case. * config.gcc (i[34567]86-*-*): Add bmi2intrin.h. (x86_64-*-*): Likewise. * config/i386/bmi2intrin.h: New file. * config/i386/cpuid.h (bit_BMI2): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect BMI2 feature. * config/i386/i386-c.c (ix86_target_macros_internal): Conditionally define __BMI2__. * config/i386/i386.c (ix86_option_override_internal): Define PTA_BMI2. Handle BMI2 option. (ix86_valid_target_attribute_inner_p): Handle BMI2 option. (print_reg): New code. (ix86_print_operand): Likewise. (ix86_builtins): Add IX86_BUILTIN_BZHI32, IX86_BUILTIN_BZHI64, IX86_BUILTIN_PDEP32, IX86_BUILTIN_PDEP64, IX86_BUILTIN_PEXT32, IX86_BUILTIN_PEXT64. (bdesc_args): Add IX86_BUILTIN_BZHI32, IX86_BUILTIN_BZHI64, IX86_BUILTIN_PDEP32, IX86_BUILTIN_PDEP64, IX86_BUILTIN_PEXT32, IX86_BUILTIN_PEXT64. * config/i386/i386.h (TARGET_BMI2): New. * config/i386/i386.md (UNSPEC_PDEP): New. (UNSPEC_PEXT): Likewise. (*bmi2_bzhi_<mode>3): Likewise. (*bmi2_pdep_<mode>3): Likewise. (*bmi2_pext_<mode>3): Likewise. * config/i386/i386.opt (mbmi2): New. * config/i386/x86intrin.h: Include bmi2intrin.h when __BMI2__ is defined. * doc/extend.texi: Document BMI2 built-in functions. * doc/invoke.texi: Document -mbmi2. gcc/testsuite/ 2011-08-23 Kirill Yukhin <kirill.yukhin@intel.com> * g++.dg/other/i386-2.C: Add -mbmi2 check. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/bmi2-bzhi32-1.c: New testcase. * gcc.target/i386/bmi2-bzhi32-1a.c: Likewise. * gcc.target/i386/bmi2-bzhi64-1.c: Likewise. * gcc.target/i386/bmi2-bzhi64-1a.c: Likewise. * gcc.target/i386/bmi2-mulx32-1.c: Likewise. * gcc.target/i386/bmi2-mulx32-1a.c: Likewise. * gcc.target/i386/bmi2-mulx64-1.c: Likewise. * gcc.target/i386/bmi2-mulx64-1a.c: Likewise. * gcc.target/i386/bmi2-pdep32-1.c: Likewise. * gcc.target/i386/bmi2-pdep32-1a.c: Likewise. * gcc.target/i386/bmi2-pdep64-1.c: Likewise. * gcc.target/i386/bmi2-pdep64-1a.c: Likewise. * gcc.target/i386/bmi2-pext32-1.c: Likewise. * gcc.target/i386/bmi2-pext32-1a.c: Likewise. * gcc.target/i386/bmi2-pext64-1.c: Likewise. * gcc.target/i386/bmi2-pext64-1a.c: Likewise. * gcc.target/i386/bmi2-rorx32-1.c: Likewise. * gcc.target/i386/bmi2-rorx32-1a.c: Likewise. * gcc.target/i386/bmi2-rorx64-1.c: Likewise. * gcc.target/i386/bmi2-rorx64-1a.c: Likewise. * gcc.target/i386/bmi2-sarx32-1.c: Likewise. * gcc.target/i386/bmi2-sarx32-1a.c: Likewise. * gcc.target/i386/bmi2-sarx64-1.c: Likewise. * gcc.target/i386/bmi2-sarx64-1a.c: Likewise. * gcc.target/i386/bmi2-shlx32-1.c: Likewise. * gcc.target/i386/bmi2-shlx32-1a.c: Likewise. * gcc.target/i386/bmi2-shlx64-1.c: Likewise. * gcc.target/i386/bmi2-shlx64-1a.c: Likewise. * gcc.target/i386/bmi2-shrx32-1.c: Likewise. * gcc.target/i386/bmi2-shrx32-1a.c: Likewise. * gcc.target/i386/bmi2-shrx64-1.c: Likewise. * gcc.target/i386/bmi2-shrx64-1a.c: Likewise. * gcc.target/i386/i386.exp (check_effective_target_bmi2): New. * gcc.target/i386/sse-12.c: Add BMI2. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178001 138bc75d-0d04-0410-961f-82ee72b054a4
* Add -mavx2.hjl2011-08-181-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | 2011-08-18 Kirill Yukhin <kirill.yukhin@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX2_SET): New. (OPTION_MASK_ISA_AVX_UNSET): Update. (OPTION_MASK_ISA_AVX2_UNSET): New. (ix86_handle_option): Handle OPT_mavx2 case. * config/i386/cpuid.h (bit_AVX2): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect AVX2 feature. * config/i386/i386-c.c (ix86_target_macros_internal): Conditionally define __AVX2__. * config/i386/i386.c (ix86_option_override_internal): Define PTA_AVX2. Define "core-avx2" processor alias. Handle avx2 option. (ix86_valid_target_attribute_inner_p): Handle avx2 option. * config/i386/i386.h (TARGET_AVX2): New. * config/i386/i386.opt (mavx2): New. * doc/invoke.texi: Document -mavx2. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@177876 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix a typo in host_detect_local_cpu.hjl2011-08-021-1/+1
| | | | | | | | | 2011-08-02 H.J. Lu <hongjiu.lu@intel.com> * config/i386/driver-i386.c (host_detect_local_cpu): Fix a typo. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@177204 138bc75d-0d04-0410-961f-82ee72b054a4
* Add -mlzcnt.hjl2011-08-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ 2011-08-01 Kirill Yukhin <kirill.yukhin@intel.com> PR target/49547 * config.gcc (i[34567]86-*-*): Replace abmintrin.h with lzcntintrin.h. (x86_64-*-*): Likewise. * config/i386/i386.opt (mlzcnt): New. * config/i386/abmintrin.h: File removed. (__lzcnt_u16, __lzcnt, __lzcnt_u64): Moved to ... * config/i386/lzcntintrin.h: ... here. New file. (__lzcnt): Rename to ... (__lzcnt32): ... this. * config/i386/bmiintrin.h (head): Update copyright year. (__lzcnt_u16): Removed. (__lzcnt_u32): Likewise. (__lzcnt_u64): Likewise. * config/i386/x86intrin.h: Include lzcntintrin.h when __LZCNT__ is defined, remove abmintrin.h. * config/i386/cpuid.h (bit_LZCNT): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect LZCNT feature. * config/i386/i386-c.c (ix86_target_macros_internal): Define __LZCNT__ if needed. * config/i386/i386.c (ix86_target_string): New option -mlzcnt. (ix86_option_override_internal): Handle LZCNT option. (ix86_valid_target_attribute_inner_p): Likewise. (struct builtin_description bdesc_args) <IX86_BUILTIN_CLZS>: Update. * config/i386/i386.h (TARGET_LZCNT): New. (CLZ_DEFINED_VALUE_AT_ZERO): Update. * config/i386/i386.md (clz<mode>2): Update insn constraint. (clz<mode>2_lzcnt): Likewise. * doc/invoke.texi: Mention -mlzcnt option. * doc/extend.texi: Likewise. gcc/testsuite/ 2011-08-01 Kirill Yukhin <kirill.yukhin@intel.com> * gcc.target/i386/i386.exp (check_effective_target_lzcnt): New. * gcc.target/i386/lzcnt-1.c: New test. * gcc.target/i386/lzcnt-2.c: Likewise. * gcc.target/i386/lzcnt-2a.c: Likewise. * gcc.target/i386/lzcnt-3.c: Likewise. * gcc.target/i386/lzcnt-4.c: Likewise. * gcc.target/i386/lzcnt-4a.c: Likewise. * gcc.target/i386/lzcnt-5.c: Likewise. * gcc.target/i386/lzcnt-6.c: Likewise. * gcc.target/i386/lzcnt-6a.c: Likewise. * gcc.target/i386/lzcnt-check.h: Likewise. * gcc.target/i386/sse-12.c (dg-compile): Add -mlzcnt. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * g++.dg/other/i386-2.C: Likewise. * g++.dg/other/i386-3.C: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@177034 138bc75d-0d04-0410-961f-82ee72b054a4
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