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* 2015-11-13 Christian Bruel <christian.bruel@st.com>chrbr2015-11-132-20/+18
* Revert [ARM] Remove neon-testgen.ml and generated tests.clyon2015-11-131-0/+324
* [ARM] Remove neon-testgen.ml and generated tests.clyon2015-11-121-324/+0
* Add initial qualcomm support.wilson2015-11-124-2/+8
* [PATCH][ARM]Fix addsi3_compare_op2 pattern.renlin2015-11-121-2/+2
* [ARM] remove unused variablecbaylis2015-11-121-6/+0
* [ARM] PR67305, tighten neon_vector_mem_operand on eliminable registersjiwang2015-11-111-3/+3
* [ARM] PR63870 Remove error for invalid lane numberscbaylis2015-11-111-40/+8
* [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifiercbaylis2015-11-112-25/+61
* [ARM] PR63870 Add qualifiers for NEON builtinscbaylis2015-11-113-18/+37
* [ARM] Fix costing of vmul+vcvt combine patternktkachov2015-11-101-0/+17
* [ARM][cleanup] Remove uses of CONST_DOUBLE_HIGH/LOWktkachov2015-11-101-24/+7
* Machine modes for address printing.jules2015-11-091-13/+5
* 2015-11-06 Michael Collison <michael.collison@linaro.orgcollison2015-11-061-38/+0
* [Patch ARM] Unified assembler in ARM state.ramana2015-11-068-274/+231
* [ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulato...ktkachov2015-11-061-0/+6
* remove unused config/arm/coff.htbsaunde2015-11-031-82/+0
* [ARM] neon-testgen.ml typojules2015-11-021-7/+7
* Fix comment typo.wilson2015-10-301-1/+1
* [ARM] Fix checking RTL error in cortex_a9_sched_adjust_costktkachov2015-10-301-3/+1
* [PATCH 8/9] ENABLE_CHECKING refactoring: target-specific partslaw2015-10-301-14/+15
* [ARM] PR target/67929 Tighten vfp3_const_double_for_bits checksktkachov2015-10-273-15/+28
* Improve --help output to generate references to option aliases.msebor2015-10-211-30/+30
* 2015-10-16 Andrew MacLeod <amacleod@redhat.com>amacleod2015-10-164-53/+21
* 2015-10-16 Christian Bruel <christian.bruel@st.com>chrbr2015-10-162-1/+23
* 2015-10-16 Christian Bruel <christian.bruel@st.com>chrbr2015-10-162-1/+23
* [PATCH][ARM]Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)<mode>_insn rtxrenlin2015-10-091-6/+6
* [Patch PR target/67366 1/2] [ARM] - Add movmisalignhi / si patternsramana2015-10-092-0/+38
* Fix PR c/65345 for armramana2015-10-071-2/+2
* * config/arm/arm.c (arm_emit_probe_stack_range): Adjust comment.ebotcazou2015-10-062-15/+14
* Remove REAL_VALUE_FROM_CONST_DOUBLErsandifo2015-10-053-57/+34
* Replace REAL_VALUES_EQUAL with real_equalrsandifo2015-10-051-3/+3
* [Patch 2/2 ARM/AArch64] Add a new Cortex-A53 scheduling modeljgreenhalgh2015-10-013-201/+664
* add separate insn sched class for vector LDP & STPspop2015-09-293-5/+17
* [Patch 1/2 AArch64/ARM] Give AArch64 ROR (Immediate) a new type attributejgreenhalgh2015-09-283-2/+4
* [ARM] Replacing variable swaps that use a temporary variable with a call to s...ktkachov2015-09-211-20/+12
* 2015-09-17 Christian Bruel <christian.bruel@st.com>chrbr2015-09-171-1/+1
* PR middle-end/65958ebotcazou2015-09-175-113/+453
* [ARM] Fix arm bootstrap failure due to -Werror=shift-negative-valuektkachov2015-09-151-4/+4
* 2015-09-15 Christian Bruel <christian.bruel@st.com>chrbr2015-09-151-0/+17
* 2015-09-15 Christian Bruel <christian.bruel@st.com>chrbr2015-09-154-77/+51
* [ARM] PR 67439: Allow matching of *arm32_movhf when -mrestrict-it is onktkachov2015-09-101-2/+3
* [ARM][3/3] Expand mod by power of 2ktkachov2015-09-092-1/+88
* [ARM] Remaining intrinsicsalalaw012015-09-085-91/+501
* [ARM] float16x8_t intrinsics in arm_neon.halalaw012015-09-081-0/+257
* [ARM] Add V8HFmode and float16x8_t typealalaw012015-09-085-2/+10
* [ARM] float16x4_t intrinsics in arm_neon.halalaw012015-09-081-0/+250
* 2015-08-26 Matthew Wahab <matthew.wahab@arm.com>mwahab2015-08-263-134/+135
* 2015-08-26 Matthew Wahab <matthew.wahab@arm.com>mwahab2015-08-261-19/+26
* 2015-08-26 Matthew Wahab <matthew.wahab@arm.com>mwahab2015-08-263-61/+82
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