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* * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi)naveenh2017-06-216-5/+8
| | | | | | | | | | | | | | | | (aarch64_crypto_pmullv2di): Change type attribute to crypto_pmull. * config/aarch64/thunderx2t99.md (thunderx2t99_pmull): New reservation. * config/arm/cortex-a57.md (cortex_a57_neon_type): Add crypto_pmull to attribute type list for neon_multiply. * config/arm/crypto.md (crypto_vmullp64): Change type to crypto_pmull. * config/arm/types.md (crypto_pmull): Add. * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to attribute type list. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249433 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macrothopre012017-06-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2017-06-20 Prakhar Bahuguna <prakhar.bahuguna@arm.com> gcc/ * config/arm/arm-c.c (arm_cpu_builtins): New block to define __ARM_FEATURE_COPROC according to support. gcc/testsuite/ * gcc.target/arm/acle/cdp.c: Add feature macro bitmap test. * gcc.target/arm/acle/cdp2.c: Likewise. * gcc.target/arm/acle/ldc.c: Likewise. * gcc.target/arm/acle/ldc2.c: Likewise. * gcc.target/arm/acle/ldc2l.c: Likewise. * gcc.target/arm/acle/ldcl.c: Likewise. * gcc.target/arm/acle/mcr.c: Likewise. * gcc.target/arm/acle/mcr2.c: Likewise. * gcc.target/arm/acle/mcrr.c: Likewise. * gcc.target/arm/acle/mcrr2.c: Likewise. * gcc.target/arm/acle/mrc.c: Likewise. * gcc.target/arm/acle/mrc2.c: Likewise. * gcc.target/arm/acle/mrrc.c: Likewise. * gcc.target/arm/acle/mrrc2.c: Likewise. * gcc.target/arm/acle/stc.c: Likewise. * gcc.target/arm/acle/stc2.c: Likewise. * gcc.target/arm/acle/stc2l.c: Likewise. * gcc.target/arm/acle/stcl.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249399 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Mark -marm and -mthumb as being inverse optionsrearnsha2017-06-161-2/+2
| | | | | | | | | | | | | -marm and -mthumb are opposites: one cancels out the other. This patch marks them as such so that the driver will eliminate all but the last option on the command line. This aids multilib selection which otherwise can get confused if both are present. * config/arm/arm.opt (marm): Mark as the negative of of -mthumb. (mthumb): Mark as the negative of -marm. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249309 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Add a few missing architecture extension options.rearnsha2017-06-162-0/+30
| | | | | | | | | | | | | | | Reviewing the list of options for the purposes of writing the documentation revealed that a small number of options were missing. Mostly these are aliases for existing options, but in a couple of cases we lacked the ability to disable certain other options. * config/arm/arm-cpus.in (armv7): Add extension +nofp. (armv7-r): Add aliases vfpv3xd and vfpv3-d16. (armv8-m.main): Add option +nodsp. * config/arm/arm-cpu-cdata.h: Regenerated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249306 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Rework multilib supportrearnsha2017-06-161-0/+33
| | | | | | | | | | | | | | | | | It looks like the fuchsia port relied on inheriting the multilib rules from the bare-metal port (the t-arm-elf makefile fragment), but that has now been rewritten on the assuption that the base architecture is ARMv4t; fuchsia has a base architecture of ARMv7-a. To account for this, I've cloned the original t-arm-elf rules into a new makefile fragment t-fuchsia and arranged for that to be used when targetting this system. * config/arm/t-fuchsia: New file. * config.gcc (arm*-*-fuchsia*): Use it. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249305 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Rework multlib builds for symbianelfrearnsha2017-06-161-2/+32
| | | | | | | | | | | | | | | | | Symbianelf used to build multilib for armv5t with softfp, but that architecture doesn't really support floating point instructions. This patch reworks the multilib configuration to use armv5te as the base when building for floating point. I'm not sure just how useful the symbian port is these days, so this has only been very lightly tested (checks that libgcc builds for all multilib variants). Perhaps we should consider deprecating this config? * config/arm/t-symbian: Rewrite for new option infrastructure. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249304 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] reset all multilib variablesrearnsha2017-06-161-9/+11
| | | | | | | | | | | | | | | | | | | | | NB. This configuration does not build in GCC-7 and doesn't build now either. This patch resets a couple of multlib variables which previously were not cleared. It almost certainly needs further work to make it use the new option framework correctly, but since the library configurations are already clearly wrong, it's not clear what the changes need to be. In particular it tries to build a hard-float library for ARM7TDMI in both ARM and thumb modes, but ARMv4t does not support any floating-point instructions; furthermore, GCC has never supported a hard-float thumb1 library. * config/arm/t-phoenix (MULTILIB_REUSE): Clear variable. (MULTILIB_REQUIRED): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249303 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Ensure all multilib variables are resetrearnsha2017-06-161-0/+4
| | | | | | | | | | | | No real change, but for consistency reset all multilib related variables. * config/arm/t-linux-eabi (MULTILIB_EXCEPTIONS): Set to empty. (MULTILIB_RESUE): Likewise. (MULTILIB_MATCHES): Likewise. (MULTLIB_REQUIRED): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249302 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Update t-rtems for new option frameworkrearnsha2017-06-161-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [This patch has only been fairly lightly tested (I've built a compiler with all the relevant multilibs and smoke-tested a few combinations to check that the tools still produce a sensible object file).] This patch updates the RTEMS build to use the new option framework. It tries as far as possible to keep the existing supported options, but there are two necessary changes and one cleanup. I've also restructed the file slightly to make it slightly easier (IMO) to understand. Necessary changes: 1: ARMv4t does not support a hard-float ABI, the earliest supported architecture with floating-point support is ARMv5te, so I've rebased the original fpu/hard libraries to that revision of the architecture. 2: Similarly, the earliest version of the -m profile to support hardware floating-point is armv7e-m (not armv7-m), so the base architecture for m-profile with FP has been correspondingly updated. Clean-up: 1: For greater consistency I've changed the -mcpu=cortex-m7/-mfpu=fpv5-d16/-mhard-float to -march=armv7e-m+fp.dp/-mhard-float. The built-in -mcpu rewrite rules take care of mapping the existing option sets onto the architecture string to ensure compatibility. Since the existing rule set does not contain any MULTILIB_REUSE rules, I have not added any here this time around, but it would be worth the maintainers of this file considering whether adding some rules would make their toolchain more friendly to users. Finally, I've added lines to reset all the multilib variables at the head of the file. I found during testing that some definitions from t-arm-elf were leaking through and causing unexpected behviour. * config/arm/t-rtems: Rewrite for new option framework. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249301 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Rewrite t-rmprofile multilib specificationrearnsha2017-06-163-138/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the R- & M-profile equivalent of the previous A-profile multilib rewrite. Additionally this patch adds some top-level rules to help find suitable multilibs for general cases when certain libraries are not built, or when building for legacy cores. gcc: * config/arm/t-aprofile (v7_a_nosimd_variants, v7_a_simd_variants) (v7ve_nosimd_variatns, v7ve_vfpv3_simd_variants) (v7ve_vfpv4_simd_variants, v8_a_nosimd_variants, v8_a_simd_variants) (v8_1_a_simd_variants, v8_2_a_simd_variants): Move to ... * config/arm/t-multilib: ... here. (MULTILIB_OPTIONS): Add armv7 and armv7+fp architectures. (MULTILIB_MATCHES): Use armv7 libraries for armv7-r. Also use for armv7-a and armv8*-a when A-profile libraries have not been built. * config/arm/t-rmprofile: Rewrite. gcc/testsuite: * gcc.target/arm/multilib.exp (rmprofile): New tests when rm-profile multilibs have been built. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249300 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Rewrite t-aprofile using new selector methodologyrearnsha2017-06-162-148/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the default FPU is 'auto' we can finally rewrite (and simplify) the rules for mapping compiler options to multilibs. We no-longer need to know the specific CPU, since the driver will construct a suitable -march flag for us; this greatly simplifies the overall logic. This patch rewrites the library list for A-profile cores. We use various Make extention rules to simplify the logic even further. A couple of minor tweaks to the configure script and to the main driver ensures that we always know the setting of -mfloat-abi and -marm/-mthumb. Again, this helps simplify the logic further. The change to arm_target_thumb_only relies on the fact that this routine is only called if neither -marm nor -mthumb has been previously selected or specified by the user. A new testsuite module is added to check the libraries generated. The new tests are only run if the compiler is configured with the relevant multilibs enabled. gcc: * config.gcc: (arm*-*-*): When building a-profile libraries, force the driver to pass through the default setting of -mfloat-abi. * common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm rather than NULL. * config/arm/t-multilib (MULTILIB_REUSE): Initialize to empty. (all_feat_combs): New rule. (MULTILIB_OPTIONS): Use explicit ARM and Thumb directories. Rework default libraries. * config/arm/t-aprofile: Rewrite. gcc/testsuite: * gcc.target/arm/multilibs.exp: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249296 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Make 'auto' the default FPU selection option.rearnsha2017-06-166-21/+4
| | | | | | | | | | | | | | | | | | | Finally, we can make 'auto' the default choice for the FPU option. It's still possible to override this during configure, but we will eventually deprecate that, moving to the new cpu/architecture selection mechanism. * config/arm/arm.h (FPUTYPE_AUTO): Define. * config/arm/arm.c (arm_option_override): Use FPUTYPE_AUTO if the fpu is not specified by the user/command-line. * config/arm/bpabi.h (FPUTYPE_DEFAULT): Delete. * config/arm/netbsd-elf.h (FPUTYPE_DEFAULT): Delete. * config/arm/linux-elf.h (FPUTYPE_DEFAULT): Delete. * config/arm/vxworks.h (FPUTYPE_DEFAULT): Delete. * common/config/arm/arm-common.c (arm_canon_arch_option): Use FPUTYPE_AUTO insted of FPUTYPE_DEFAULT. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249295 138bc75d-0d04-0410-961f-82ee72b054a4
* [genmultilib] Update basic multilib configurationrearnsha2017-06-162-73/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | The standard arm-eabi configuration comes with a basic set of multilibs that are suitable mostly for simple testing of the compiler in various configurations. We try to keep the number of libraries build small so that build times do not become too onerous. Using the new auto-fp selection code we can now cover all supported architectures except for those with single-precision only FP units with just 4 multilibs. This is done with the rewrite of t-arm-elf. Now that we canonicalize -mcpu into suitable -march definitions we don't need to match CPU names to architectures any more; the driver will do this for us. I also noticed whilst writing this patch that the existing MULTILIB_DEFAULTS setting in the compiler was causing more problems than it was worth; and furthermore was simply wrong if the compiler is ever configured with --with-mode, --with-float or --with-endian. The remaining options also pertained to pre-eabi builds and aren't interesting today either. It seemed best to just delete the definition entirely. * config/arm/elf.h (MULTILIB_DEFAULTS): Delete. * config/arm/t-arm-elf: Rewritten. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249294 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Make -mfloat-abi=softfp work when there are norearnsha2017-06-163-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch series it wasn't really possible to not have an FPU; it was always there, even if the hardware didn't really support it. Now that we have -mfpu=auto, the concept of not having an FPU becomes real. Consequently, when the -mfloat-abi switch is set to softfp doing the Right Thing is much more important. In this case we have a soft-float ABI, but can use FP instructions if they are available. To support this we have to separate out TARGET_HARD_FLOAT into two use cases: one where the instructions exist and one when they don't. We preserve the original meaning of TARGET_HARD_FLOAT (but add an extra check) of meaning that we are generating HW FP instructions, and add a new macro for the special case when use of FP instructions is permitted, but might not be available at this time (the distinction is important because they might be enabled by an attribute during the compilation). TARGET_SOFT_FLOAT continues to be the exact inverse of TARGET_HARD_FLOAT, but we now define it as such. * config/arm/arm.h (TARGET_HARD_FLOAT): Also check that we have some floating-point instructions. (TARGET_SOFT_FLOAT): Define as inverse of TARGET_HARD_FLOAT. (TARGET_MAYBE_HARD_FLOAT): New macro. * config/arm/arm-builtins.c (arm_init_builtins): Use TARGET_MAYBE_HARD_FLOAT. * config/arm/arm.c (arm_option_override): Use TARGET_HARD_FLOAT_ABI. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249293 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Generate a canonical form for -marchrearnsha2017-06-161-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the driver and some spec rewrite rules to generate a canonicalized form of the -march= option. We want to do this for several reasons, all relating to making multi-lib selection sane. 1) It can remove redundant extension options to produce a minimal list. 2) The general syntax of the option permits a plethora of features, these are permitted in any order. Canonicalization ensures that there is a single ordering of the options that are needed. 3) It can use additional options to remove extensions that aren't relevant, such as removing all features that relate to the FPU when use of that is disabled. Once we have this information in a sensible form the multilib rules can be vastly simplified making for much more understandable Makefile fragments. * common/config/arm/arm-common.c: Define INCLUDE_LIST. (configargs.h): Include it. (arm_print_hint_for_fpu_option): New function. (arm_parse_fpu_option): New function. (candidate_extension): New class. (arm_canon_for_multilib): New function. * config/arm/arm.h (CANON_ARCH_SPEC_FUNCTION): New macro. (EXTRA_SPEC_FUNCTIONS): Add CANON_ARCH_SPEC_FUNCTION. (ARCH_CANONICAL_SPECS): New macro. (DRIVER_SELF_SPECS): Add ARCH_CANONICAL_SPECS. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249292 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Allow new extended syntax CPU and architecturerearnsha2017-06-162-9/+35
| | | | | | | | | | | | | | | | | | | | This patch extends support for the new extended-style architecture strings to configure and the target default options. We validate any options passed by the user to configure against the permitted extensions for that CPU or architecture. * config.gcc (arm*-*-fucshia*): Set target_cpu_cname to the real cpu name. (arm*-*-*): Set target_cpu_default2 to a quoted string. * config/arm/parsecpu.awk (check_cpu): Validate any extension options. (check_arch): Likewise. * config/arm/arm.c (arm_configure_build_target): Handle TARGET_CPU_DEFAULT being a string constant. Scan any feature options in the default. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249290 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Allow CPU and architecture extensions to berearnsha2017-06-165-297/+435
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A follow up patch to this one will start to canonicalize options to simplify generating multilib fragments. This patch is enabling work for that. If we have extension options that duplicate other options (done principally for back-wards compatibility purposes) we need to ensure that just one of them will be used consistently when generating a canonical form of the user-specified options. We do this by explicitly noting when an option is defined as an alias of another. Another aspect of canonicalization is to enforce a strict order in which the options are inspected, we do this by ensuring that no later option examined can be a subset of an earlier option (add and remove options are treated separtely). It's practically impossible to check all this in parsecpu.awk since that premits use of C macros in the ISA features list, so instead we enforce the ordering with a selftest function in the compiler, which is only run when self tests are enabled (it's not something that will change every day, so this should be sufficient). * config/arm/arm-protos.h (cpu_arch_extension): Add field to record when an option is an alias of another. * config/arm/parsecpu.awk (optalias): New parser token. (gen_comm_data): Mark non-alias options as such. Emit entries for extension aliases. * config/arm/arm-cpus.in (armv5e): Make vfpv2 an alias. (armv5te, armv5tej, armv6, armv6j, armv6k, armv6z): Likewise. (armv6kz, armv6zk, armv6t2): Likewise. (armv7): Make vfpv3-d16 an alias. (armv7-a): Make vfpv3-d16, neon and neon-vfpv3 aliases. Sort in canonical order. (armv7ve): Make vfpv4-d16, neon-vfpv3 and neon-vfpv4 aliases. Sort in canonical order. (armv8-a): Sort in canonical order. (armv8.1-a, armv8.2-a): Likewise. (generic-armv7-a): Make neon and neon-vfpv3 aliases. Sort in canonical order. (cortex-a9): Sort in canonical order. * config/arm/arm.c (selftests.h): Include it. (arm_test_cpu_arch_data): New function. (arm_run_self_tests): New function. (TARGET_RUN_TARGET_SELFTESTS): Redefine. (targetm): Move declaration to the end of the file. * arm-cpu-cdata.h: Regenerated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249289 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Use standard option parsing code for detectingrearnsha2017-06-163-1117/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the standard CPU and architecture option parsing code is available in the driver we can use the main CPU and architecture data tables for driving the automatic enabling of Thumb code. Doing this requires that the driver script tell the parser whether or not the target string is a CPU name or an architecture, but beyond that it is just standard use of the new capabilities. We do, however, now get some error checking if the target isn't recognized, when previously we just ignored unknown targets and hoped that a later pass would pick up on this. * config/arm/arm.h (TARGET_MODE_SPECS): Add additional parameter to call to target_mode_check describing the type of option passed. * common/config/arm/arm-common.c (arm_arch_core_flag): Delete. (arm_target_thumb_only): Use arm_parse_arch_option_name or arm_parse_cpu_option_name to match parameters against list of available targets. * config/arm/parsecpu.awk (gen_comm_data): Don't generate arm_arch_core_flags data structure. * config/arm/arm-cpu_cdata.h: Regenerated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249288 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Move cpu and architecture option name parsingrearnsha2017-06-165-2760/+2629
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has no functional change. The code used for parsing -mcpu, -mtune and -march options is simply moved from arm.c arm-common.c. The list of FPU options is also moved. Subsequent patches will make use of this within the driver. Some small adjustments are needed as a consequence of moving the definitions of the data objects to another object file, in that we no-longer have direct access to the size of the object. * common/config/arm/arm-common.c (arm_initialize_isa): Moved here from config/arm/arm.c. (arm_print_hint_for_cpu_option): Likewise. (arm_print_hint_for_arch_option): Likewise. (arm_parse_cpu_option_name): Likewise. (arm_parse_arch_option_name): Likewise. * config/arm/arm.c (arm_identify_fpu_from_isa): Use the computed number of entries in the all_fpus list. * config/arm/arm-protos.h (all_architectures, all_cores): Declare. (arm_parse_cpu_option_name): Declare. (arm_parse_arch_option_name): Declare. (arm_parse_option_features): Declare. (arm_intialize_isa): Declare. * config/arm/parsecpu.awk (gen_data): Move CPU and architecture data tables to ... (gen_comm_data): ... here. Make definitions non-static. * config/arm/arm-cpu-data.h: Regenerated. * config/arm/arm-cpu-cdata.h: Regenerated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249287 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Split CPU, architecture and tuning data tables.rearnsha2017-06-165-1287/+1840
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver really needs to handle some canonicalization of the new -mcpu and -march options in order to make multilib selection tractable. This will require moving much of the logic to parse the new options into the common code file. However, the tuning data definitely does not want to be there as it is very specific to the compiler passes. To facilitate this we need to split up the generated configuration data into architectural and tuning related tables. This patch starts that process, but does not yet move any code out of the compiler backend. Since I'm reworking all that code I took the opportunity to also separate out the CPU data tables from the architecture data tables. Although they are related, there is a lot of redundancy in the CPU options that is best handled by simply indirecting to the architecture entry. * config/arm/arm-protos.h (arm_build_target): Remove arch_core. (cpu_arch_extension): New structure. (cpu_arch_option, arch_option, cpu_option): New structures. * config/arm/parsecpu.awk (gen_headers): Build an enumeration of architecture types. (gen_data): Generate new format data tables. * config/arm/arm.c (cpu_tune): New structure. (cpu_option, processors): Delete. (arm_print_hint_for_core_or_arch): Delete. Replace with ... (arm_print_hint_for_cpu_option): ... this and ... (arm_print_hint_for_arch_option): ... this. (arm_parse_arch_cpu_name): Delete. Replace with ... (arm_parse_cpu_option_name): ... this and ... (arm_parse_arch_option_name): ... this. (arm_unrecognized_feature): Change type of target parameter to cpu_arch_option. (arm_parse_arch_cpu_features): Delete. Replace with ... (arm_parse_option_features): ... this. (arm_configure_build_target): Rework to use new configuration data tables. (arm_print_tune_info): Rework for new configuration data tables. * config/arm/arm-cpu-data.h: Regenerated. * config/arm/arm-cpu.h: Regenerated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249286 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Add default FPUs for CPUs.rearnsha2017-06-165-164/+692
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the default CPUs for each cpu and provides options for changing the FPU variant when appropriate. It turns out to be easier to describe removal options using general mask operations that disable a concept rather than specific bits. Sometimes the helper definitions for enabling a feature are not excat duals when it comes to disabling them - for example, +simd forcibly turns on double-precision capabilities in the FPU, but disabling just simd (+nosimd) should not forcibly disable that. * config/arm/arm-isa.h (ISA_ALL_FPU_INTERNAL): Renamed from ISA_ALL_FPU. (ISA_ALL_CRYPTO): New macro. (ISA_ALL_SIMD): New macro (ISA_ALL_FP): New macro. * config/arm/arm.c (fpu_bitlist): Update initializer. * config/arm/arm-cpus.in: Use new ISA_ALL macros to disable crypto, simd or fp. (arm9e): Add fpu. Add option for nofp (arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e): Likewise. (arm926ej-s, arm1026ej-s): Likewise. (generic-armv7-a): Add fpu. Add options for simd, vfpv3, vfpv3-d16, vfpv3-fp16, vfpv3-d16-fp16, vfpv4, vfpv4-d16, neon, neon-vfp3, neon-fp16, neon-vfpv4, nofp and nosimd. (cortex-a5, cortex-a7): Add fpu. Add options for nosimd and nofp. (cortex-a8): Add fpu. Add option for nofp. (cortex-a9): Add fpu. Add options for nosimd and nofp. (cortex-a12, cortex-a15, cortex-a17): Add fpu. Add option for nofp. (cortex-r4f): Add fpu. (cortex-r5): Add fpu. Add options for nofp.dp and nofp. (cortex-r7): Use idiv option from architecture. Add fpu. Add option for nofp. (cortex-r8): Likewise. (cortex-m4): Add fpu. Add option for nofp. (cortex-a15.cortex-a7): Add fpu. Add option for nofp. (cortex-a17.cortex-a7): Likewise. (cortex-a32): Add fpu. Add options for crypto and nofp. (cortex-a35, cortex-a53): Likewise. (cortex-a57): Add fpu. Add option for crypto. (cortex-a72, cortex-a73): Likewise. (exynos-m1): Likewise. (cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise. (cortex-a73.cortex-a35, cortex-a73.cortex-a53): Likewise. (cortex-m33): Add fpu. Add option for nofp. * config/arm/arm-cpu-cdata.h: Regenerated * config/arm/arm-cpu-data.h: Regenerated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249284 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Add architectural optionsrearnsha2017-06-162-15/+458
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the currently supported architecture options to the individual architectures. For floating point and SIMD we only permit variants that the relevant versions of the architecture permit. We also add short-hand versions (+fp, +simd, etc) that allows the user to describe using floating point without having to know the precise version of the floating point sub-architecture that that architecture requires. In a small number of cases we need to provide more precise versions of the floating point architecture. In those cases we permit traditional -mfpu style names in the architecture description. * arm-cpus.in (armv5e): Add options fp, vfpv2 and nofp. (armv5te, armv5tej): Likewise. (armv6, armv6j, armv6k, armv6z, armv6kz, armv6zk, armv6t2): Likewise. (armv7): Add options fp and vfpv3-d16. (armv7-a): Add options fp, simd, vfpv3, vfpv3-d16, vfpv3-d16-fp16, vfpv3-fp16, vfpv4, vfpv4-d16, neon, neon-vfpv3, neon-fp16, neon-vfpv4, nofp and nosimd. (armv7ve): Likewise. (armv7-r): Add options fp, fp.sp, idiv, nofp and noidiv. (armv7e-m): Add options fp, fpv5, fp.dp and nofp. (armv8-a): Add nocrypto option. (armv8.1-a, armv8.2-a): Likewise. (armv8-m.main): add options fp, fp.dp and nofp. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249283 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Allow +opt on arbitrary cpu and architecturerearnsha2017-06-166-158/+547
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the main patch to provide the infrastructure for adding feature extensions to CPU and architecture specifications. It does not, however, add all the extensions that we intend to support (just a small number to permit some basic testing). Now, instead of having specific entries in the architecture table for variants such as armv8-a+crc, the crc extension is specified as an optional component of the armv8-a architecture entry. Similar control can be added to CPU option names. In both cases the list of permitted options is controlled by the main architecture or CPU name to prevent arbitrary cross-products of options. * config/arm/arm-cpus.in (armv8-a): Add options crc, simd crypto and nofp. (armv8-a+crc): Delete. (armv8.1-a): Add options simd, crypto and nofp. (armv8.2-a): Add options fp16, simd, crypto and nofp. (armv8.2-a+fp16): Delete. (armv8-m.main): Add option dsp. (armv8-m.main+dsp): Delete. (cortex-a8): Add fpu. Add nofp option. (cortex-a9): Add fpu. Add nofp and nosimd options. * config/arm/parsecpu.awk (gen_data): Generate option tables and link to main cpu and architecture data structures. (gen_comm_data): Only put isa attributes from the main architecture in common tables. (option): New statement for architecture and CPU entries. * arm.c (struct cpu_option): New structure. (struct processors): Add entry for options. (arm_unrecognized_feature): New function. (arm_parse_arch_cpu_name): Ignore any characters after the first '+' character. (arm_parse_arch_cpu_feature): New function. (arm_configure_build_target): Separate out any CPU and architecture features and parse separately. Don't error out if -mfpu=auto is used with only an architecture string. (arm_print_asm_arch_directives): New function. (arm_file_start): Call it. * config/arm/arm-cpu-cdata.h: Regenerated. * config/arm/arm-cpu-data.h: Likewise. * config/arm/arm-tables.opt: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249282 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Don't pass -mfpu=auto through to the assembler.rearnsha2017-06-161-1/+1
| | | | | | | | | | | | The assembler doesn't understand -mfpu=auto. The easiest way to handle this is to surpress this value from being passed through, while still passing through legacy values. * config/arm/elf.h (ASM_SPEC): Only pass -mfpu through to the assembler when it is not -mfpu=auto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249281 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Rewrite -march and -mcpu options for passing torearnsha2017-06-161-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The assembler does not understand all the '+' options accepted by the compiler. The best solution to this is to simply strip the extensions and just pass the raw architecture or cpu name through to the assembler. We will use .arch and .arch_extension directives anyway to turn on or off individual features. We already do something similar for big.little combinations and this just extends this principle a bit further. This patch also fixes a possible bug by ensuring that the limited string copy is correctly NUL-terminated. While messing with this code I've also taken the opportunity to clean up the duplicate definitions of EXTRA_SPEC_FUNCTIONS by moving it outside of the ifdef wrapper. * config/arm/arm.h (BIG_LITTLE_SPEC): Delete macro. (ASM_REWRITE_SPEC_FUNCTIONS): New macro. (BIG_LITTLE_CPU_SPEC_FUNCTIONS): Delete macro. (ASM_CPU_SPEC): Rewrite. (MCPU_MTUNE_NATIVE_FUNCTIONS): New macro. (EXTRA_SPEC_FUNCTIONS): Move outside of ifdef. Use MCPU_MTUNE_NATIVE_FUNCTIONS and ASM_REWRITE_SPEC_FUNCTIONS. Remove reference to BIG_LITTLE_CPU_SPEC_FUNCTIONS. * common/config/arm/arm-common.c (arm_rewrite_selected_cpu): Ensure copied string is NUL-terminated. Also strip any characters prefixed by '+'. (arm_rewrite_selected_arch): New function. (arm_rewrite_march): New function. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249280 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] Use strings for -march, -mcpu and -mtune optionsrearnsha2017-06-162-13/+94
| | | | | | | | | | | | | | | | | | | | | | | | | In order to support more complex specifications for cpus and architectures we need to move away from using enumerations to represent the set of permitted options. This basic change just moves the option parsing infrastructure over to that, but changes nothing more beyond generating a hint when the specified option does not match a known target (previously the help option was able to print out all the permitted values, but we can no-longer do that. * config/arm/arm.opt (x_arm_arch_string): New TargetSave option. (x_arm_cpu_string, x_arm_tune_string): Likewise. (march, mcpu, mtune): Convert to string-based options. * config/arm/arm.c (arm_print_hint_for_core_or_arch): New function. (arm_parse_arch_cpu_name): New function. (arm_configure_build_target): Use arm_parse_arch_cpu_name to identify selected architecture or CPU. (arm_option_save): New function. (TARGET_OPTION_SAVE): Redefine. (arm_option_restore): Restore string options. (arm_option_print): Print string options. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249279 138bc75d-0d04-0410-961f-82ee72b054a4
* [Patch ARM] Fix PR71778jgreenhalgh2017-06-161-1/+6
| | | | | | | | | | | | | | | | | | gcc/ PR target/71778 * config/arm/arm-builtins.c (arm_expand_builtin_args): Return TARGET if given a non-constant argument for an intrinsic which requires a constant. gcc/testsuite/ PR target/71778 * gcc.target/arm/pr71778.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249272 138bc75d-0d04-0410-961f-82ee72b054a4
* Improve Cortex-A53 FP schedulerwilco2017-06-141-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | The Cortex-A53 scheduler model of FMAC bypass is not quite right for FMAC to FMAC forwarding. Experiments also show the latencies of FP operations are too high as well. Rather than adding more bypasses, adjust the latencies of FP instructions to get a better schedule on average. As a result SPECFP2006 is 1.1% faster. gcc/ * config/arm/cortex-a53.md (cortex_a53_fpalu) Adjust latency. (cortex_a53_fconst): Likewise. (cortex_a53_fpmul): Likewise. (cortex_a53_f_load_64): Likewise. (cortex_a53_f_load_many): Likewise. (cortex_a53_advsimd_alu): Likewise. (cortex_a53_advsimd_alu_q): Likewise. (cortex_a53_advsimd_mul): Likewise. (cortex_a53_advsimd_mul_q): Likewise. (fpmac bypass): Add new bypass for fpmac-fpmac case. Add missing fmul, r2f_cvt and fconst cases. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249200 138bc75d-0d04-0410-961f-82ee72b054a4
* 2017-06-09 Tamar Christina <tamar.christina@arm.com>tnfchris2017-06-091-1/+7
| | | | | | | | | | | | | * config/arm/arm.c (arm_rtx_costs_internal): Make sdiv more expensive than udiv. gcc/testsuite/ 2017-06-09 Tamar Christina <tamar.christina@arm.com> * gcc.target/arm/sdiv_costs_1.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249062 138bc75d-0d04-0410-961f-82ee72b054a4
* 2017-06-07 Tamar Christina <tamar.christina@arm.com>tnfchris2017-06-071-1/+1
| | | | | | | | * config/arm/aarch-cost-tables.h (cortexa53_extra_cost): Increase idiv cost. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248951 138bc75d-0d04-0410-961f-82ee72b054a4
* Remove aarch32 support for falkor/qdf24xx, not in released hardware.wilson2017-06-0711-194/+3
| | | | | | | | | | | | | | | | | | | | | gcc/ * config/aarch64/aarch64-cost-tables.h (qdf24xx_extra_costs): Move to here. * config/arm/aarch-cost-tables.h (qdf24xx_extra_costs): From here. * config/arm/arm-cpu-cdata.h: Regenerate. * config/arm/arm-cpu-data.h, config/arm/arm-cpu.h: Likewise. * config/arm/arm-tables.opt, config/arm/arm-tune.md: Likewise. * config/arm/arm-cpus.in: Delete falkor and qdf24xx entries. * config/arm/arm.c (arm_qdf24xx_tune): Delete. * config/arm/bpabi.h (BE8_LINK_SPEC): Delete falkor and qdf24xx support. * config/arm/t-aprofile (MULTILIB_MATCHES): Delete falkor and qdf24xx support. * config/arm/t-rmprofile: Likewise. * doc/invoke.texi (ARM Options): Drop falkor and qdf24xx support. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248944 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Rename *_compute_save_reg_mask ()thopre012017-06-061-9/+9
| | | | | | | | | | | | | | 2017-06-06 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.c (arm_compute_save_reg_mask): Rename into ... (arm_compute_save_core_reg_mask): This. (thumb1_compute_save_reg_mask): Rename into ... (thumb1_compute_save_core_reg_mask): This. (arm_compute_save_reg0_reg12_mask): Adapt comment. (arm_compute_frame_layout): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248920 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Complete legend for ARM register allocation in arm.hthopre012017-06-051-1/+1
| | | | | | | | | | 2017-06-05 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.h: explain F symbol found in description of ARM register allocation in its legend. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248880 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix ARM bootstrap failure due to an odd warning:wilco2017-05-301-3/+3
| | | | | | | | | | | | | | | | | /src/gcc/gcc/config/arm/arm-builtins.c: In function 'rtx_def* arm_expand_builtin(tree, rtx, rtx, machine_mode, int)': /src/gcc/gcc/config/arm/arm-builtins.c:3056:46: error: type qualifiers ignored on cast result type [-Werror=ignored-qualifiers] if (d->code == (const enum arm_builtins) fcode) ^~~~~ Avoid the warning by removing const, and bootstrap is OK again. Committed as trivial patch. gcc/ * config/arm/arm-builtins.c (arm_expand_builtin): Remove const. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248686 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Fix typo in comment in arm_expand_prologuethopre012017-05-241-1/+1
| | | | | | | | | 2017-05-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.c (arm_expand_prologue): Fix typo in comment. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248419 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix comment for cmse_nonsecure_call_clear_caller_savedthopre012017-05-171-3/+4
| | | | | | | | | | | 2017-05-17 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.c (cmse_nonsecure_call_clear_caller_saved): Refer readers to __gnu_cmse_nonsecure_call libcall for saving, clearing and restoring of callee-saved registers. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248142 138bc75d-0d04-0410-961f-82ee72b054a4
* Committed on behalf of Matthew Wahabtnfchris2017-05-162-2/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ 2017-05-16 Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm_neon.h (vadd_f16): Use standard arithmetic operations in fast-math mode. (vaddq_f16): Likewise. (vmul_f16): Likewise. (vmulq_f16): Likewise. (vsub_f16): Likewise. (vsubq_f16): Likewise. * config/arm/neon.md (add<mode>3): New. (sub<mode>3): New. (fma:<VH:mode>3): New. Also remove outdated comment. (mul<mode>3): New. testsuite/ 2017-05-16 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/arm/armv8_2-fp16-arith-1.c: Expand comment. Update expected output of vadd, vsub and vmul instructions. * gcc.target/arm/armv8_2-fp16-arith-2.c: New. * gcc.target/arm/armv8_2-fp16-neon-2.c: New. * gcc.target/arm/armv8_2-fp16-neon-3.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248090 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Add missing TARGET_32BIT conditional to movsithopre012017-05-121-2/+2
| | | | | | | | | | | 2017-05-12 Prakhar Bahuguna <prakhar.bahuguna@arm.com> gcc/ * config/arm/arm.md (movsi): Add TARGET_32BIT in addition to the TARGET_HAVE_MOVT conditional. (movt splitter): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247971 138bc75d-0d04-0410-961f-82ee72b054a4
* 2017-05-08 Bernd Edlinger <bernd.edlinger@hotmail.de>edlinger2017-05-081-9/+25
| | | | | | | | | | | | | | | | * target.def (compute_frame_layout): New optional target hook. * doc/tm.texi.in (TARGET_COMPUTE_FRAME_LAYOUT): Add hook. * doc/tm.texi (TARGET_COMPUTE_FRAME_LAYOUT): Add documentation. * lra-eliminations.c (update_reg_eliminate): Call compute_frame_layout target hook. * reload1.c (verify_initial_elim_offsets): Likewise. * config/arm/arm.c (TARGET_COMPUTE_FRAME_LAYOUT): Define. (use_simple_return_p): Call arm_compute_frame_layout if needed. (arm_get_frame_offsets): Split up into this ... (arm_compute_frame_layout): ... and this function. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247750 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Allow combination of aprofile and rmprofile multilibsthopre012017-05-053-46/+83
| | | | | | | | | | | | | | | | | | | | | 2017-05-05 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config.gcc: Allow combinations of aprofile and rmprofile values for --with-multilib-list. * config/arm/t-multilib: New file. * config/arm/t-aprofile: Remove initialization of MULTILIB_* variables. Remove setting of ISA and floating-point ABI in MULTILIB_OPTIONS and MULTILIB_DIRNAMES. Set architecture and FPU in MULTI_ARCH_OPTS_A and MULTI_ARCH_DIRS_A rather than MULTILIB_OPTIONS and MULTILIB_DIRNAMES respectively. Add comment to introduce all matches. Add architecture matches for marvel-pj4 and generic-armv7-a CPU options. * config/arm/t-rmprofile: Likewise except for the matches changes. * doc/install.texi (--with-multilib-list): Document the combination of aprofile and rmprofile values and warn about pitfalls in doing that. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247646 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] PR71607: Fix ICE when loading constantthopre012017-05-053-11/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2017-05-05 Andre Vieira <andre.simoesdiasvieira@arm.com> Prakhar Bahuguna <prakhar.bahuguna@arm.com> gcc/ PR target/71607 * config/arm/arm.md (use_literal_pool): Remove. (64-bit immediate split): No longer takes cost into consideration if arm_disable_literal_pool is enabled. * config/arm/arm.c (arm_tls_referenced_p): Add diagnostic if TLS is used when arm_disable_literal_pool is enabled. (arm_max_const_double_inline_cost): Remove use of arm_disable_literal_pool. (push_minipool_fix): Add assert. (arm_reorg): Add return if arm_disable_literal_pool is enabled. * config/arm/vfp.md (no_literal_pool_df_immediate): New. (no_literal_pool_sf_immediate): New. 2017-05-05 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> Prakhar Bahuguna <prakhar.bahuguna@arm.com> gcc/testsuite/ PR target/71607 * gcc.target/arm/thumb2-slow-flash-data.c: Renamed to ... * gcc.target/arm/thumb2-slow-flash-data-1.c: ... this. * gcc.target/arm/thumb2-slow-flash-data-2.c: New. * gcc.target/arm/thumb2-slow-flash-data-3.c: New. * gcc.target/arm/thumb2-slow-flash-data-4.c: New. * gcc.target/arm/thumb2-slow-flash-data-5.c: New. * gcc.target/arm/tls-disable-literal-pool.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247640 138bc75d-0d04-0410-961f-82ee72b054a4
* Code scheduling for Cortex-A53 isn't as good as it could be. It turns outwilco2017-05-053-0/+48
| | | | | | | | | | | | | | | | | | | | code runs faster overall if we place loads and stores with a dependency closer together. To achieve this effect, this patch adds a bypass between cortex_a53_load1 and cortex_a53_load*/cortex_a53_store* if the result of an earlier load is used in an address calculation. This significantly improved benchmark scores in a proprietary benchmark suite. gcc/ * config/arm/aarch-common.c (arm_early_load_addr_dep_ptr): New function. (arm_early_store_addr_dep_ptr): Likewise. * config/arm/aarch-common-protos.h (arm_early_load_addr_dep_ptr): Add prototype. (arm_early_store_addr_dep_ptr): Likewise. * config/arm/cortex-a53.md: Add new bypasses. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247631 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Enable Purecode for ARMv8-M Baselinethopre012017-05-042-31/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for purecode to ARMv8-M Baseline, in addition to the existing support for ARMv7-M and ARMv8-M Mainline. 2017-05-04 Prakhar Bahuguna <prakhar.bahuguna@arm.com> Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com> gcc/ * config/arm/arm.md (movsi): Change TARGET_32BIT to TARGET_HAVE_MOVT. (movt splitter): Likewise. * config/arm/arm.c (arm_option_check_internal): Change arm_arch_thumb2 to TARGET_HAVE_MOVT, and merge with -mslow-flash-data check. (const_ok_for_arm): Change else to else if (TARGET_THUMB2) and add else block for Thumb-1 with MOVT. (thumb2_legitimate_address_p): Move code block ... (can_avoid_literal_pool_for_label_p): ... into this new function. (thumb1_legitimate_address_p): Add check for TARGET_HAVE_MOVT and literal pool. (thumb_legitimate_constant_p): Add conditional on TARGET_HAVE_MOVT * doc/invoke.texi (-mpure-code): Change "ARMv7-M targets" for "M-profile targets with the MOVT instruction". gcc/testsuite/ * gcc.target/arm/pure-code/pure-code.exp: Add conditional for check_effective_target_arm_thumb1_movt_ok. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247585 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Rename FPSCR builtins to correct namesthopre012017-05-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The GCC documentation in section 6.60.8 ARM Floating Point Status and Control Intrinsics states that the FPSCR register can be read and written to using the intrinsics __builtin_arm_get_fpscr and __builtin_arm_set_fpscr. However, these are misnamed within GCC itself and these intrinsic names are not recognised. This patch corrects the intrinsic names to match the documentation, and adds tests to verify these intrinsics generate the correct instructions. 2017-05-04 Prakhar Bahuguna <prakhar.bahuguna@arm.com> gcc/ * gcc/config/arm/arm-builtins.c (arm_init_builtins): Rename __builtin_arm_ldfscr to __builtin_arm_get_fpscr, and rename __builtin_arm_stfscr to __builtin_arm_set_fpscr. gcc/testsuite/ * gcc.target/arm/fpscr.c: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247584 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Set mode for success result of atomic compare and swapthopre012017-05-033-14/+36
| | | | | | | | | | | | | | | | 2017-05-03 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/iterators.md (CCSI): New mode iterator. (arch): New mode attribute. * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Rename into ... (atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): This and ... (atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): This. Use CCSI code iterator for success result mode. * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use the corresponding new insn generators. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247542 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/77728jakub2017-04-251-17/+61
| | | | | | | | | | | | | | | | | | | | | * config/arm/arm.c: Include gimple.h. (aapcs_layout_arg): Emit -Wpsabi note if arm_needs_doubleword_align returns negative, increment ncrn only if it returned positive. (arm_needs_doubleword_align): Return int instead of bool, ignore DECL_ALIGN of non-FIELD_DECL TYPE_FIELDS chain members, but if there is any such non-FIELD_DECL > PARM_BOUNDARY aligned decl, return -1 instead of false. (arm_function_arg): Emit -Wpsabi note if arm_needs_doubleword_align returns negative, increment nregs only if it returned positive. (arm_setup_incoming_varargs): Likewise. (arm_function_arg_boundary): Emit -Wpsabi note if arm_needs_doubleword_align returns negative, return DOUBLEWORD_ALIGNMENT only if it returned positive. testsuite/ * g++.dg/abi/pr77728-1.C: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247258 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Fix type for .init_array.* and .fini_array.* sectionsthopre012017-04-201-1/+1
| | | | | | | | | | | 2017-04-20 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.c (arm_elf_asm_cdtor): Create non-default priority .init_array and .fini_array section with SECTION_NOTYPE flag. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247015 138bc75d-0d04-0410-961f-82ee72b054a4
* [arm] PR 80389 - if architecture and cpu mismatch, don't print an ↵rearnsha2017-04-111-2/+2
| | | | | | | | | | | | | | | | architecture name as a CPU name In this PR we incorrectly print the architecture name in a .cpu directive in the assembly file when the -mcpu and -march options conflict (don't target the same base architecture). In this case the .arch overrides the .cpu directive and we should emit a .arch option. PR target/80389 * config/arm/arm.c (arm_configure_build_target): When -mcpu and -arch conflict, set target->arch_name instead of target->cpu_name. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246843 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Add source mode to coprocessor pattern SETsktkachov2017-04-101-2/+2
| | | | | | | | * config/arm/arm.md (<mrc>): Add mode to SET source. (<mrrc>): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246801 138bc75d-0d04-0410-961f-82ee72b054a4
* ARM: Introduce ARM_DEFAULT_SHORT_ENUMSsh2017-04-073-2/+9
| | | | | | | | | | | | | | | Allow targets to define the default for the short enums option. gcc/ * config/arm/arm.h (ARM_DEFAULT_SHORT_ENUMS): Provide default definition. * config/arm/arm.c (arm_default_short_enums): Use ARM_DEFAULT_SHORT_ENUMS. * config/arm/rtems.h (ARM_DEFAULT_SHORT_ENUMS): Define. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246753 138bc75d-0d04-0410-961f-82ee72b054a4
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