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* * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi)naveenh2017-06-216-5/+8
* [ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macrothopre012017-06-201-0/+16
* [arm] Mark -marm and -mthumb as being inverse optionsrearnsha2017-06-161-2/+2
* [arm] Add a few missing architecture extension options.rearnsha2017-06-162-0/+30
* [arm] Rework multilib supportrearnsha2017-06-161-0/+33
* [arm] Rework multlib builds for symbianelfrearnsha2017-06-161-2/+32
* [arm] reset all multilib variablesrearnsha2017-06-161-9/+11
* [arm] Ensure all multilib variables are resetrearnsha2017-06-161-0/+4
* [arm] Update t-rtems for new option frameworkrearnsha2017-06-161-17/+32
* [arm] Rewrite t-rmprofile multilib specificationrearnsha2017-06-163-138/+117
* [arm] Rewrite t-aprofile using new selector methodologyrearnsha2017-06-162-148/+111
* [arm] Make 'auto' the default FPU selection option.rearnsha2017-06-166-21/+4
* [genmultilib] Update basic multilib configurationrearnsha2017-06-162-73/+104
* [arm] Make -mfloat-abi=softfp work when there are norearnsha2017-06-163-6/+10
* [arm] Generate a canonical form for -marchrearnsha2017-06-161-1/+19
* [arm] Allow new extended syntax CPU and architecturerearnsha2017-06-162-9/+35
* [arm] Allow CPU and architecture extensions to berearnsha2017-06-165-297/+435
* [arm] Use standard option parsing code for detectingrearnsha2017-06-163-1117/+1
* [arm] Move cpu and architecture option name parsingrearnsha2017-06-165-2760/+2629
* [arm] Split CPU, architecture and tuning data tables.rearnsha2017-06-165-1287/+1840
* [arm] Add default FPUs for CPUs.rearnsha2017-06-165-164/+692
* [arm] Add architectural optionsrearnsha2017-06-162-15/+458
* [arm] Allow +opt on arbitrary cpu and architecturerearnsha2017-06-166-158/+547
* [arm] Don't pass -mfpu=auto through to the assembler.rearnsha2017-06-161-1/+1
* [arm] Rewrite -march and -mcpu options for passing torearnsha2017-06-161-21/+21
* [arm] Use strings for -march, -mcpu and -mtune optionsrearnsha2017-06-162-13/+94
* [Patch ARM] Fix PR71778jgreenhalgh2017-06-161-1/+6
* Improve Cortex-A53 FP schedulerwilco2017-06-141-18/+16
* 2017-06-09 Tamar Christina <tamar.christina@arm.com>tnfchris2017-06-091-1/+7
* 2017-06-07 Tamar Christina <tamar.christina@arm.com>tnfchris2017-06-071-1/+1
* Remove aarch32 support for falkor/qdf24xx, not in released hardware.wilson2017-06-0711-194/+3
* [ARM] Rename *_compute_save_reg_mask ()thopre012017-06-061-9/+9
* [ARM] Complete legend for ARM register allocation in arm.hthopre012017-06-051-1/+1
* Fix ARM bootstrap failure due to an odd warning:wilco2017-05-301-3/+3
* [ARM] Fix typo in comment in arm_expand_prologuethopre012017-05-241-1/+1
* Fix comment for cmse_nonsecure_call_clear_caller_savedthopre012017-05-171-3/+4
* Committed on behalf of Matthew Wahabtnfchris2017-05-162-2/+74
* [ARM] Add missing TARGET_32BIT conditional to movsithopre012017-05-121-2/+2
* 2017-05-08 Bernd Edlinger <bernd.edlinger@hotmail.de>edlinger2017-05-081-9/+25
* [ARM] Allow combination of aprofile and rmprofile multilibsthopre012017-05-053-46/+83
* [ARM] PR71607: Fix ICE when loading constantthopre012017-05-053-11/+56
* Code scheduling for Cortex-A53 isn't as good as it could be. It turns outwilco2017-05-053-0/+48
* [ARM] Enable Purecode for ARMv8-M Baselinethopre012017-05-042-31/+53
* [ARM] Rename FPSCR builtins to correct namesthopre012017-05-041-2/+2
* [ARM] Set mode for success result of atomic compare and swapthopre012017-05-033-14/+36
* PR target/77728jakub2017-04-251-17/+61
* [ARM] Fix type for .init_array.* and .fini_array.* sectionsthopre012017-04-201-1/+1
* [arm] PR 80389 - if architecture and cpu mismatch, don't print an architectur...rearnsha2017-04-111-2/+2
* [ARM] Add source mode to coprocessor pattern SETsktkachov2017-04-101-2/+2
* ARM: Introduce ARM_DEFAULT_SHORT_ENUMSsh2017-04-073-2/+9
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