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* merge adjust_cost and adjust_cost_2 target hookstbsaunde2016-07-282-19/+23
* 2016-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-142-5/+10
* 2016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-133-11/+105
* 2016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-134-43/+81
* gcc/nathan2016-07-121-4/+14
* 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-074-8/+11
* 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-071-24/+25
* 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-076-9/+38
* 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-071-2/+3
* [ARM] Add support for some ARMv8-A cores to driver-arm.cktkachov2016-07-061-0/+6
* This patch improves the accuracy of the Cortex-A53 integer scheduler, wilco2016-07-061-61/+48
* [ARM][testsuite] neon-testgen.ml removalclyon2016-07-052-2681/+0
* [ARM] Delete thumb_reload_in_hktkachov2016-07-012-8/+0
* * config/arm/arm.c (arm_function_ok_for_sibcall): Add another checkebotcazou2016-07-011-1/+1
* Add qdf24xx base tuning support.wilson2016-06-293-1/+127
* [ARM][1/4] Replace uses of int_log2 by exact_log2ktkachov2016-06-241-19/+7
* 2016-06-23 Jakub Sejdak <jakub.sejdak@phoesys.com>ksejdak2016-06-231-0/+29
* [ARM] Add initial support for Cortex-A73ktkachov2016-06-226-2/+48
* [AArch64] Give some new costs for Cortex-A53 floating-point operationsjgreenhalgh2016-06-201-26/+26
* [AArch64] Give some new costs for Cortex-A57 floating-point operationsjgreenhalgh2016-06-201-26/+26
* The Cortex-A57 scheduler is missing fcsel, so add it.wilco2016-06-201-1/+1
* [Patch ARM arm_neon.h] s/__FAST_MATH/__FAST_MATH__/gjgreenhalgh2016-06-171-6/+6
* 2016-06-14 Andreas Tobler <andreast@gcc.gnu.org>andreast2016-06-141-0/+4
* [ARM] length pop* pattern in epilogue correctlyjiwang2016-06-113-4/+70
* 2016-06-10 Bernd Edlinger <bernd.edlinger@hotmail.de>edlinger2016-06-101-5/+0
* [AArch64] Model CSEL instruction in Cortex-A57 scheduling modelktkachov2016-06-091-1/+1
* [1/3][ARM] Keep ctz expressions together until after reloadktkachov2016-06-061-11/+14
* [ARM][obvious] Fix typos in *thumb1_mulsi3 commentktkachov2016-06-031-5/+5
* Fix fallout from: [ARM] PR target/70830: Avoid POP-{reglist}^ when returning ...ktkachov2016-06-021-4/+2
* [ARM] Use proper output modifier for DImode register in store exclusive patternsktkachov2016-06-011-9/+6
* [ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMCktkachov2016-06-013-3/+24
* 2016-05-31 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-05-313-3/+12
* 2016-05-27 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-05-271-3/+0
* [ARM][4/4] Simplify checks for CONST_INT_P and comparison against 1/0ktkachov2016-05-242-4/+3
* [ARM][3/4] Cleanup casts from INTVAL to [unsigned] HOST_WIDE_INTktkachov2016-05-244-24/+20
* [ARM][2/4] Replace casts of 1 to HOST_WIDE_INT by HOST_WIDE_INT_1 and HOST_WI...ktkachov2016-05-243-13/+13
* [ARM] PR target/69857 Remove bogus early return false; in gen_operands_ldrd_strdktkachov2016-05-241-8/+10
* [ARM, AArch64] Add missing vtst_p16 and vtstq_p16, and vtst_p{8,16} and vtstq...clyon2016-05-231-0/+12
* * config/arm/arm.c (arm_expand_prologue): Set the stack usage to 0ebotcazou2016-05-201-2/+10
* [ARM] Fix costing of sign-extending load in rtx costsktkachov2016-05-191-2/+0
* [ARM] PR target/71056: Don't use vectorized builtins when NEON is not availablektkachov2016-05-191-1/+5
* [ARM] Enable __fp16 as a function parameter and return type.mwahab2016-05-165-46/+29
* Fix PR target/53440 - handle generic thunks better for TARGET_32BIT.ramana2016-05-131-5/+91
* [ARM] PR target/70830: Avoid POP-{reglist}^ when returning from interrupt han...ktkachov2016-05-121-8/+11
* [ARM] Add mode to probe_stack set operandsktkachov2016-05-091-2/+2
* Emit vmov.i64 to load 0.0 into FP reg when neon enabled.wilson2016-05-072-23/+35
* 2016-04-25 Michael Collison <michael.collison@linaro.org>collison2016-04-254-52/+201
* * tree.h (TYPE_ALIGN, DECL_ALIGN): Return shifted amount.matz2016-04-181-2/+2
* PR target/70711mwahab2016-04-181-0/+6
* [ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsl...ktkachov2016-04-081-2/+4
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