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* Update copyright years.jakub2018-01-031-1/+1
* Remove vec_perm_const optabrsandifo2018-01-021-1/+0
* This patch adds support for modelling the varying costs ofcbaylis2017-11-231-0/+20
* 2017-11-10 Tamar Christina <tamar.christina@arm.com>tnfchris2017-11-101-0/+2
* Turn FUNCTION_ARG_PADDING into a target hookrsandifo2017-09-041-1/+0
* Turn MODES_TIEABLE_P into a target hookrsandifo2017-09-041-1/+0
* Turn HARD_REGNO_MODE_OK into a target hookrsandifo2017-09-041-1/+0
* Remove enum before machine_modersandifo2017-07-051-1/+1
* [arm] Fix incorrect __ARM_ARCH_PROFILE for -march=armv7rearnsha2017-06-281-0/+4
* [arm] Allow CPU and architecture extensions to berearnsha2017-06-161-0/+6
* [arm] Move cpu and architecture option name parsingrearnsha2017-06-161-0/+12
* [arm] Split CPU, architecture and tuning data tables.rearnsha2017-06-161-2/+36
* Fix PR80082: LDRD erronously used for 64bit load on ARMv7-Rthopre012017-03-221-2/+2
* PR target/79260rearnsha2017-01-301-2/+0
* [ARM] Implement support for ACLE Coprocessor LDC and STC intrinsicsavieira2017-01-061-0/+1
* [ARM] Implement support for ACLE Coprocessor CDP intrinsicsavieira2017-01-061-1/+2
* Update copyright years.jakub2017-01-011-1/+1
* [arm] Use cl_target_options for configuring the active targetrearnsha2016-12-151-1/+1
* [arm] Initialize fpu capability bits in arm_active_targetrearnsha2016-12-151-0/+4
* [arm] Remove insn_flags.rearnsha2016-12-151-4/+3
* [arm] Introduce arm_active_target.rearnsha2016-12-151-0/+25
* This patch adds the new ISA data structures. The idea is to use anrearnsha2016-12-151-0/+1
* We start out by separating the 'tuning flags' in a CPU or architecturerearnsha2016-12-151-1/+1
* ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_callavieira2016-12-021-0/+1
* ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and bxnsavieira2016-12-021-0/+1
* [ARM] Optional -mthumb for Thumb only targetsthopre012016-11-181-186/+2
* Make arm_feature_set agree with type of FL_* macrosthopre012016-11-181-45/+46
* [ARM][2/2] Remove old rtx costsktkachov2016-11-081-1/+0
* [PATCH 1/17][ARM] Add ARMv8.2-A command line option and profile.mwahab2016-09-231-0/+4
* 2016-08-24 Michael Collison <michael.collison@linaro.org>collison2016-08-241-0/+2
* merge adjust_cost and adjust_cost_2 target hookstbsaunde2016-07-281-1/+1
* 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-071-24/+25
* 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-07-071-0/+2
* [ARM] Delete thumb_reload_in_hktkachov2016-07-011-1/+0
* [ARM] length pop* pattern in epilogue correctlyjiwang2016-06-111-0/+1
* [ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMCktkachov2016-06-011-0/+1
* 2016-05-31 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012016-05-311-0/+3
* 2016-04-25 Michael Collison <michael.collison@linaro.org>collison2016-04-251-1/+3
* Enable instruction fusion of AES instructions on ARM for Cortex-A53 andwilco2016-02-101-2/+3
* [ARM] Remove neon_reinterpret, use castsalalaw012016-02-041-1/+0
* 2016-01-20 Christian Bruel <christian.bruel@st.com>chrbr2016-01-271-0/+1
* gccchrbr2016-01-151-1/+0
* Update copyright years.jakub2016-01-041-1/+1
* [ARM] Add support for ARMv8.1.mwahab2015-12-161-0/+3
* [ARM] PR target/68214: Delete IP-reg-clobbering call-through-mem patternsktkachov2015-12-041-1/+0
* Make builtin_vectorized_function take a combined_fnrsandifo2015-11-171-1/+1
* 2015-11-16 Christian Bruel <christian.bruel@st.com>chrbr2015-11-161-0/+1
* PR middle-end/65958ebotcazou2015-09-171-0/+1
* 2015-09-15 Christian Bruel <christian.bruel@st.com>chrbr2015-09-151-1/+0
* 2015-08-26 Matthew Wahab <matthew.wahab@arm.com>mwahab2015-08-261-2/+2
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