delta/gcc.git - gcc.gnu.org: git/gcc.git

	Commit message (Expand)	Author	Age	Files	Lines
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*	[AArch64] Do not increase data alignment at -Os and with -fconserve-stack.	ramana	2017-06-28	1	-8/+18
*	This patch fixes a failure in gcc.target/aarch64/reload-valid-spoff.c	wilco	2017-06-28	1	-0/+4
*	2017-06-19 Michael Collison <michael.collison@arm.com>	collison	2017-06-27	2	-61/+33
*	* config/aarch64/aarch64.c (aarch64_emit_probe_stack_range): Handle	law	2017-06-22	1	-5/+13
*	2017-06-21 Andrew Pinski <apinski@cavium.com>	pinskia	2017-06-21	3	-12/+58
*	2017-06-21 Andrew Pinski <apinski@cavium.com>	pinskia	2017-06-21	2	-7/+50
*	[AArch64] Fix atomic_cmp_exchange_zero_reg_1.c with +lse	ktkachov	2017-06-21	1	-4/+4
*	Emit SIMD moves as mov	wilco	2017-06-21	2	-4/+4
*	Improve dup pattern	wilco	2017-06-21	1	-4/+4
*	Mark symbols as constant	wilco	2017-06-21	1	-0/+5
*	[Patch AArch64] Add initial tuning support for Cortex-A55 and Cortex-A75	jgreenhalgh	2017-06-21	2	-1/+11
*	* config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi)	naveenh	2017-06-21	2	-2/+9
*	[Patch AArch64] Add rcpc extension	jgreenhalgh	2017-06-20	2	-0/+4
*	[Patch AArch64 obvious] Fix expected string for fp16 extensions	jgreenhalgh	2017-06-20	1	-1/+1
*	[Patch AArch64 obvious] Rearrange the processors in aarch64-cores.def	jgreenhalgh	2017-06-20	2	-12/+14
*	Update prefetch tuning parameters for qdf24xx.	mkuvyrkov	2017-06-16	1	-4/+4
*	Enable -fprefetch-loop-arrays at given optimization level.	mkuvyrkov	2017-06-16	2	-4/+18
*	Add prefetch configuration to aarch64 backend.	mkuvyrkov	2017-06-16	2	-28/+90
*	PR target/71663	naveenh	2017-06-14	1	-4/+51
*	2017-06-09 Tamar Christina <tamar.christina@arm.com>	tnfchris	2017-06-09	1	-0/+12
*	2017-06-07 Tamar Christina <tamar.christina@arm.com>	tnfchris	2017-06-07	1	-8/+6
*	2017-06-07 Tamar Christina <tamar.christina@arm.com>	tnfchris	2017-06-07	1	-4/+6
*	Remove aarch32 support for falkor/qdf24xx, not in released hardware.	wilson	2017-06-07	1	-3/+105
*	[AArch64] Allow const0_rtx operand for atomic compare-exchange patterns	ktkachov	2017-06-06	1	-4/+4
*	[AArch64] Add combine pattern for storing lane zero of a vector	ktkachov	2017-06-05	1	-0/+13
*	[AArch64] Use SUBS for parallel subtraction and comparison with immediate	ktkachov	2017-06-05	2	-0/+35
*	[AArch64] Peephole for SUBS	ktkachov	2017-06-05	1	-0/+18
*	[PATCH][AArch64] Allow CMP+SHIFT when comparing with zero	jgreenhalgh	2017-06-02	1	-1/+1
*	[AArch64] Add HF vector modes to lane-to-lane INS pattern	ktkachov	2017-06-02	1	-5/+5
*	[AArch64] Emit tighter strong atomic compare-exchange loop when comparing aga...	ktkachov	2017-06-02	1	-6/+35
*	[PATCH][AARCH64]Simplify call, call_value, sibcall, sibcall_value patterns.	renlin	2017-05-15	4	-129/+65
*	Move an use-after-free access before the delete.	wilco	2017-05-10	1	-2/+2
*	[AArch64] Tighten move constraints for symbolic operands	rsandifo	2017-05-08	2	-2/+10
*	Float to int moves currently generate inefficient code due to	wilco	2017-05-05	1	-4/+4
*	Many supported cores use the AUTOPREFETCHER_WEAK setting which tries	wilco	2017-05-04	1	-1/+1
*	Set jump alignment to 4 for Cortex cores as it reduces codesize by 0.4% on	wilco	2017-05-04	1	-5/+5
*	With -mcpu=generic the loop alignment is currently 4. All but one of the	wilco	2017-05-04	1	-2/+2
*	All cores which add a cpu_addrcost_table use a non-zero value for	wilco	2017-05-04	1	-2/+2
*	[AArch64] Accept more addressing modes for PRFM	ktkachov	2017-05-04	5	-10/+41
*	[AArch64] Fix for gcc-7 regression PR 80530	rearnsha	2017-04-27	1	-22/+29
*	PR target/77728	jakub	2017-04-27	1	-69/+21
*	PR target/77728	jakub	2017-04-25	1	-26/+75
*	* config/aarch64/thunderx2t99.md (thunderx2t99_crc): New Reservation.	naveenh	2017-04-25	1	-0/+7
*	* config/aarch64/thunderx2t99.md (thunderx2t99_aes): New Reservation.	naveenh	2017-04-25	1	-0/+13
*	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Fix	naveenh	2017-04-25	1	-1/+1
*	2017-04-08 Andreas Tobler <andreast@gcc.gnu.org>	andreast	2017-04-08	1	-0/+5
*	2017-04-07 Andreas Tobler <andreast@gcc.gnu.org>	andreast	2017-04-07	1	-0/+3
*	Error message on target attribute on aarch64 target (PR target/79889).	marxin	2017-04-07	1	-2/+6
*	PR target/78002	ebotcazou	2017-04-05	2	-23/+20
*	Recently we've put a lot of effort into improving ifcvt to use CSEL on AArch64.	wilco	2017-03-22	1	-2/+2