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* Turn MODES_TIEABLE_P into a target hookrsandifo2017-09-043-13/+11
* Turn HARD_REGNO_MODE_OK into a target hookrsandifo2017-09-043-8/+8
* Turn HARD_REGNO_CALL_PART_CLOBBERED into a target hookrsandifo2017-09-042-6/+14
* PR82045: Avoid passing machine modes through "..."rsandifo2017-09-042-2/+2
* [AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>jgreenhalgh2017-08-311-2/+2
* 2017-08-31 Tamar Christina <tamar.christina@arm.com>tnfchris2017-08-311-1/+1
* [AArch64] Tighten address register subreg checksrsandifo2017-08-311-2/+6
* [AArch64] Rename cmp_result iteratorrsandifo2017-08-313-88/+88
* [AArch64] Remove use of wider vector modesrsandifo2017-08-314-277/+34
* [73/77] Pass scalar_mode to scalar_mode_supported_prsandifo2017-08-301-2/+2
* [72/77] Pass scalar_mode to scalar_mode_supported_prsandifo2017-08-301-1/+1
* [62/77] Big machine_mode to scalar_int_mode replacementrsandifo2017-08-301-1/+1
* [20/77] Replace MODE_INT checks with is_int_modersandifo2017-08-301-8/+12
* [18/77] Make int_mode_for_mode return an opt_scalar_int_modersandifo2017-08-301-5/+8
* [14/77] Make libgcc_floating_mode_supported_p take a scalar_float_modersandifo2017-08-301-1/+1
* [7/77] Add scalar_float_modersandifo2017-08-301-2/+6
* [2/77] Add an E_ prefix to case statementsrsandifo2017-08-303-249/+249
* [1/77] Add an E_ prefix to mode namesrsandifo2017-08-302-29/+29
* [AArch64] Fix label modersandifo2017-08-221-1/+1
* [AArch64] Improve SIMD store of zero.rearnsha2017-08-171-22/+28
* 2017-08-12 Andrew Pinski <apinski@cavium.com>pinskia2017-08-131-1/+1
* 2017-08-11 Tamar Christina <tamar.christina@arm.com>tnfchris2017-08-112-8/+3
* Add falkor pipeline description.wilson2017-08-093-2/+684
* 2017-08-08 Tamar Christina <tamar.christina@arm.com>tnfchris2017-08-082-0/+65
* .marxin2017-08-081-0/+1
* [AArch64] Use gen_frame_mem for callee-saveswilco2017-08-071-12/+8
* 2017-08-02 Tamar Christina <tamar.christina@arm.com>tnfchris2017-08-021-3/+8
* 2017-08-01 Tamar Christina <tamar.christina@arm.com>tnfchris2017-08-011-4/+4
* PR target/80846jakub2017-08-012-4/+15
* 2017-07-28 Tamar Christina <tamar.christina@arm.com>tnfchris2017-07-282-6/+32
* 2017-07-28 Tamar Christina <tamar.christina@arm.com>tnfchris2017-07-283-26/+71
* 2017-07-28 Tamar Christina <tamar.christina@arm.com>tnfchris2017-07-284-46/+183
* [PATCH][AArch64] Fix missing optimization for CMP+ANDjgreenhalgh2017-07-272-0/+40
* 2017-07-26 Andrew Pinski <apinski@cavium.com>pinskia2017-07-261-2/+2
* 2017-07-26 Andrew Pinski <apinski@cavium.com>pinskia2017-07-261-1/+1
* [Patch AArch64 obvious] Unify address costs to generic_addrcost_tablejgreenhalgh2017-07-261-36/+4
* [Patch AArch64 Obvious] Unify branch costs to generic_branch_costjgreenhalgh2017-07-261-20/+6
* [RTEMS] Add GCC Runtime Library Exceptionsh2017-07-251-6/+11
* PR target/81414amker2017-07-251-4/+11
* Fix PR79041wilco2017-07-241-1/+1
* [AArch64, Patch] Generate MLA when multiply + add vector by scalarjgreenhalgh2017-07-241-0/+24
* Add RDMA support to falkor port.wilson2017-07-214-6/+12
* * profile-count.h (profile_probability::from_reg_br_prob_note,hubicka2017-07-161-3/+1
* [Patch][Aarch64] Refactor comments in aarch64_print_operandjgreenhalgh2017-07-141-17/+32
* 2017-07-11 Michael Collison <michael.collison@arm.com>collison2017-07-121-0/+11
* 2017-07-07 Andrew Pinski <apinski@cavium.com>pinskia2017-07-071-1/+3
* Remove enum before machine_modersandifo2017-07-054-25/+25
* 2017-06-29 Julian Brown <julian@codesourcery.com>naveenh2017-06-302-1/+46
* 2017-06-29 Naveen H.S <Naveen.Hurugalawadi@cavium.com>naveenh2017-06-301-7/+17
* 2017-06-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>collison2017-06-293-14/+131
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