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* [AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STPktkachov2016-08-011-2/+4
* 2016-08-01 Virendra Pathak <virendra.pathak@broadcom.com>rearnsha2016-08-011-1/+1
* On AArch64 the UXTB and UXTH instructions are aliases of UBFM,wilco2016-07-283-11/+18
* This patchset improves zero extend costs and code generation.wilco2016-07-281-5/+6
* This patch improves the readability of the prolog and epilog code by movingwilco2016-07-281-36/+35
* [AArch64][10/10] ARMv8.2-A FP16 lane scalar intrinsicsjiwang2016-07-251-0/+52
* [AArch64][9/10] ARMv8.2-A FP16 three operands scalar intrinsicsjiwang2016-07-253-10/+27
* [AArch64][8/10] ARMv8.2-A FP16 two operands scalar intrinsicsjiwang2016-07-255-63/+311
* [AArch64][7/10] ARMv8.2-A FP16 one operand scalar intrinsicsjiwang2016-07-257-57/+498
* [AArch64][6/14] ARMv8.2-A FP16 reduction vector intrinsicsjiwang2016-07-254-12/+65
* [AArch64][5/10] ARMv8.2-A FP16 lane vector intrinsicsjiwang2016-07-253-16/+173
* [AArch64][4/10] ARMv8.2-A FP16 three operands vector intrinsicsjiwang2016-07-253-15/+43
* [AArch64][3/10] ARMv8.2-A FP16 two operands vector intrinsicsjiwang2016-07-255-94/+482
* [AArch64][2/10] ARMv8.2-A FP16 one operand vector intrinsicsjiwang2016-07-256-59/+483
* [AArch64][1/10] ARMv8.2-A FP16 data processing intrinsicsjiwang2016-07-253-15/+298
* [AArch64][3/3] Migrate aarch64_expand_prologue/epilogue to aarch64_add_constantjiwang2016-07-251-63/+24
* [AArch64][2/3] Optimize aarch64_add_constant to generate better addition sequ...jiwang2016-07-251-38/+41
* [AArch64][1/3] Migrate aarch64_add_constant to new interface & kill aarch64_b...jiwang2016-07-251-90/+13
* [PATCH/AARCH64] Add rtx_costs routine for vulcan.jgreenhalgh2016-07-153-1/+178
* [AArch64] Use fmin/fmax for v[min|max]nm{q} intrinsicsjiwang2016-07-082-8/+12
* [AArch64] Renaming ARMv8.1 to ARMv8.1-A in comments and documentationsjiwang2016-07-044-6/+6
* [AArch64] Fix PR target/63874ramana2016-07-041-4/+8
* [AArch64] ARMv8.2 command line and feature macros supportjiwang2016-07-044-2/+23
* This patch sets the branch cost to the same most optimal setting for all Cortexwilco2016-06-301-6/+6
* [AArch64][2/2] (Re)Implement vcopy<q>_lane<q> intrinsicsktkachov2016-06-301-156/+392
* [AArch64][1/2] Add support INS (element) instruction to copy lanes between ve...ktkachov2016-06-301-0/+43
* Add qdf24xx base tuning support.wilson2016-06-292-1/+52
* Increase loop alignment on Cortex cores to 8 and set function alignment to 16.wilco2016-06-291-7/+7
* * config/aarch64/aarch64-protos.h (aarch64_elf_asm_named_section):schwab2016-06-221-1/+0
* [AArch64] Add initial support for Cortex-A73ktkachov2016-06-223-2/+30
* [PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCCjgreenhalgh2016-06-212-1/+5
* This patch cleans up the -mpc-relative-loads option processing. Rename to avoidwilco2016-06-202-36/+32
* [Patch AArch64] Add some more missing intrinsicsjgreenhalgh2016-06-201-0/+53
* [Patch AArch64] Fixup to fcvt patterns added in r237200jgreenhalgh2016-06-203-16/+12
* Improve modes_tieable by returning true in more cases: allow scalar accesswilco2016-06-201-4/+14
* [AArch64] Handle iterator definitions with conditionals in geniterator.shnsz2016-06-171-6/+15
* [PATCH][AARCH64]Fix typo in aarch64_legitimize_address.renlin2016-06-161-1/+1
* [AArch64][obvious] Clean up parentheses and use GET_MODE_UNIT_BITSIZE in a co...ktkachov2016-06-151-14/+8
* [AArch64] Handle AND+ASHIFT form of UBFIZ correctly in costsktkachov2016-06-143-11/+37
* [AArch64] Emit division using the Newton seriesevandro2016-06-135-5/+128
* [AArch64] Emit square root using the Newton seriesevandro2016-06-135-39/+112
* [AArch64] Add more choices for the reciprocal square root approximationevandro2016-06-133-10/+54
* [PATCH 1/2][AArch64] Implement AAPCS64 updates for alignment attributejgreenhalgh2016-06-081-15/+16
* [AArch64, 6/6] Reimplement vpadd intrinsics & extend rtl patterns to all modesjiwang2016-06-083-55/+39
* [AArch64, 5/6] Reimplement fabd intrinsics & merge rtl patternsjiwang2016-06-083-71/+49
* [AArch64, 4/6] Reimplement frsqrts intrinsicsjiwang2016-06-084-61/+48
* [AArch64, 3/6] Reimplement frsqrte intrinsicsjiwang2016-06-084-72/+47
* [AArch64, 2/6] Reimplement vector fixed-point intrinsicsjiwang2016-06-084-148/+106
* [AArch64, 1/6] Reimplement scalar fixed-point intrinsicsjiwang2016-06-085-98/+113
* [2/3][AArch64] Keep CTZ components together until after reloadktkachov2016-06-061-9/+16