delta/gcc.git - gcc.gnu.org: git/gcc.git

	Commit message (Expand)	Author	Age	Files	Lines
*	[AArch64] Restore gimple_folding of reduction intrinsics	alalaw01	2014-10-27	2	-23/+11
*	[AArch64] Use new reduc_[us](min\|max)_scal optabs, inc. for builtins	alalaw01	2014-10-27	3	-90/+82
*	[AArch64] Use new reduc_plus_scal optabs, inc. for __builtins	alalaw01	2014-10-27	4	-53/+60
*	2014-10-27 Andrew MacLeod <amacleod@redhat.com>	amacleod	2014-10-27	2	-1/+23
*	[AArch64] Temporarily remove aarch64_gimple_fold_builtin code for reduction o...	alalaw01	2014-10-27	2	-2/+6
*	[PATCH 2/2] [AARCH64,NEON] Convert arm_neon.h to use new builtins for vld[234...	cbaylis	2014-10-24	1	-125/+281
*	[PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in...	cbaylis	2014-10-24	4	-0/+107
*	[AArch64] LINK_SPEC changes for Cortex-A53 erratum 835769 workaround	ktkachov	2014-10-24	2	-2/+20
*	[AArch64] Cleanup logic around aarch64_final_prescan	ktkachov	2014-10-24	2	-20/+33
*	PR target/63173	fyang	2014-10-24	4	-120/+942
*	2014-10-21 Andrew Pinski <apinski@cavium.com>	pinskia	2014-10-21	4	-2/+152
*	2014-10-16 Andrew MacLeod <amacleod@redhat.com>	amacleod	2014-10-16	1	-1/+5
*	* config/aarch64/aarch64.c (aarch64_legitimize_address): New function.	rearnsha	2014-10-16	1	-0/+44
*	[AARCH64] Add ACLE 2.0 predefined macros	jiwang	2014-10-15	1	-2/+16
*	[AArch64] Remove unused variable and marco	jiwang	2014-10-15	1	-4/+0
*	[AArch64] Add --enable-fix-cortex-a53-835769 configure-time option	ktkachov	2014-10-10	2	-1/+10
*	[AArch64] Implement workaround for ARM Cortex-A53 erratum 835769	ktkachov	2014-10-10	4	-0/+137
*	[AArch64] Wire up vqdmullh_laneq_s16 and vqdmullh_laneq_s32	jgreenhalgh	2014-09-30	3	-4/+16
*	2014-09-26 Christophe Lyon <christophe.lyon@linaro.org>	clyon	2014-09-26	2	-0/+17
*	[AArch64] Tighten predicates on SIMD shift intrinsics	jgreenhalgh	2014-09-25	5	-42/+81
*	[AArch64] Improve regmove_costs for 128-bit types.	jiwang	2014-09-24	1	-8/+21
*	[AArch64] Use __aarch64_vget_lane* macros for getting the lane in some lane m...	ktkachov	2014-09-24	1	-4/+4
*	[AArch64] Enable shrink wrapping.	mshawcroft	2014-09-23	3	-0/+34
*	[AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c	jgreenhalgh	2014-09-22	4	-120/+57
*	[PATCH AArch64]: Add constraint letter for stack_protect_test pattern	jgreenhalgh	2014-09-19	1	-1/+1
*	[AArch64] Add regmove_costs for Cortex-A57 and A53	jiwang	2014-09-12	1	-2/+22
*	[AArch64] Fix cost for Q register moves	jiwang	2014-09-12	1	-5/+2
*	[AArch64] Add cost handling of CALLER_SAVE_REGS and POINTER_REGS	jiwang	2014-09-12	1	-0/+7
*	[AArch64] Simplify vreinterpret for float64x1_t using casts.	alalaw01	2014-09-11	7	-203/+20
*	[AArch64] Replace temporary inline assembler for vset_lane	alalaw01	2014-09-11	1	-312/+168
*	[AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32}	jgreenhalgh	2014-09-11	1	-4/+4
*	recog_memoized works on an rtx_insn *	dmalcolm	2014-09-09	2	-2/+2
*	Add crtfastmath for AArch64.	ramana	2014-09-09	2	-1/+11
*	[AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant la...	ktkachov	2014-09-09	2	-15/+19
*	[Obvious] Remove unused aarch64_types_cmtst_qualifiers, was breaking bootstrap.	alalaw01	2014-09-08	1	-5/+0
*	Fix PR63190	vekumar	2014-09-07	1	-2/+2
*	[PATCH AArch64] Rename [u]int32x1_t to [u]int32_t (resp 16x1, 8x1) in arm_neon.h	alalaw01	2014-09-05	1	-223/+217
*	[PATCH AArch64 2/2] Replace temporary inline assembler for vget_high	alalaw01	2014-09-05	1	-132/+79
*	[PATCH AArch64 2/2] Remove vector compare/tst __builtins	alalaw01	2014-09-05	3	-306/+160
*	[PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instruction	alalaw01	2014-09-05	6	-60/+114
*	[PATCH][AArch64] Tidy: remove unused qualifier_const_pointer	alalaw01	2014-09-05	1	-3/+1
*	[PATCH][AArch64] One-liner: fix type of an add in SIMD registers	alalaw01	2014-09-05	1	-1/+1
*	[PATCH AArch64] Remove varargs from aarch64_simd_expand_args	alalaw01	2014-09-05	1	-13/+3
*	[PATCH AArch64] Add a builtin for rbit(q?)_p8; add intrinsics and tests.	alalaw01	2014-09-05	3	-44/+49
*	[AArch64 Obvious] Add a mode to operand 1 of sibcall_value_insn	jgreenhalgh	2014-09-05	1	-1/+2
*	PR target/62040	carrot	2014-09-04	2	-4/+42
*	aarch64: Improve epilogue unwind info	rth	2014-09-03	1	-182/+78
*	[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions.	ktkachov	2014-09-02	4	-51/+69
*	NEXT_INSN and PREV_INSN take a const rtx_insn	dmalcolm	2014-08-28	1	-1/+1
*	PR target/62262	carrot	2014-08-27	1	-1/+2