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path: root/gcc/config/aarch64/constraints.md
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* Update copyright years.Jakub Jelinek2020-01-011-1/+1
* aarch64: Add "c" constraintRichard Henderson2019-11-141-0/+4
* [AArch64] Add support for arm_sve.hRichard Sandiford2019-10-291-0/+68
* [AArch64] Use scvtf fbits option where appropriateJoel Hutton2019-08-191-0/+7
* [AArch64] Rework SVE INC/DEC handlingRichard Sandiford2019-08-151-1/+7
* [AArch64] Use SVE binary immediate instructions for conditional arithmeticRichard Sandiford2019-08-151-1/+1
* [AArch64] Make more use of SVE conditional constant movesRichard Sandiford2019-08-141-1/+7
* [AArch64] Add support for SVE F{MAX,MIN}NM immediateRichard Sandiford2019-08-141-1/+8
* [AArch64] Add support for SVE [SU]{MAX,MIN} immediateRichard Sandiford2019-08-141-3/+9
* [AArch64] Improve SVE constant movesRichard Sandiford2019-08-131-0/+6
* [AArch64] Add a "y" constraint for V0-V7Richard Sandiford2019-08-131-0/+3
* [AArch64] Fix INSR for zero floatsRichard Sandiford2019-08-071-2/+2
* Update copyright years.Jakub Jelinek2019-01-011-1/+1
* [AARCH64] Use STLUR for atomic_storeMatthew Malcomson2018-09-191-0/+5
* [Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bi...Sam Tebbs2018-09-131-0/+7
* [AArch64][PATCH 1/2] Fix addressing printing of LDP/STPAndre Vieira2018-07-191-13/+7
* [AArch64] PR target/85512: Tighten SIMD right shift immediate constraints pt2Kyrylo Tkachov2018-04-271-2/+2
* [AArch64] PR target/85512: Tighten SIMD right shift immediate constraintsKyrylo Tkachov2018-04-241-0/+14
* [PR83370][AARCH64]Use tighter register constraint for sibcall patterns.Renlin Li2018-02-011-2/+2
* [AArch64] PR82964: Fix 128-bit immediate ICEsWilco Dijkstra2018-01-171-0/+6
* [AArch64] SVE load/store_lanes supportRichard Sandiford2018-01-131-0/+6
* [AArch64] Add SVE supportRichard Sandiford2018-01-131-6/+114
* aarch64-modes.def (V2HF): New VECTOR_MODE.Michael Collison2018-01-111-0/+12
* [AArch64] Rewrite aarch64_simd_valid_immediateRichard Sandiford2018-01-031-6/+5
* Update copyright years.Jakub Jelinek2018-01-031-1/+1
* [AArch64] Tweak aarch64_classify_address interfaceRichard Sandiford2017-12-211-7/+7
* [AArch64] Add STP pattern to store a vec_concat of two 64-bit registersKyrylo Tkachov2017-11-081-0/+9
* vec_merge + vec_duplicate + vec_concat simplificationKyrylo Tkachov2017-11-081-0/+7
* [AArch64] Rename the internal "Upl" constraintRichard Sandiford2017-11-011-1/+1
* [PATCH][AArch64] Add BIC-imm and ORR-imm SIMD patternSudakshina Das2017-10-041-0/+14
* [AArch64, PATCH] Improve Neon store of zeroJackson Woodruff2017-09-131-0/+8
* 2017-07-28 Tamar Christina <tamar.christina@arm.com>Tamar Christina2017-07-281-2/+16
* [PATCH][AARCH64]Simplify call, call_value, sibcall, sibcall_value patterns.Renlin Li2017-05-151-1/+2
* [AArch64] Tighten move constraints for symbolic operandsRichard Sandiford2017-05-081-0/+8
* [AArch64] Accept more addressing modes for PRFMKyrylo Tkachov2017-05-041-0/+5
* Update copyright years.Jakub Jelinek2017-01-011-1/+1
* 2016-11-22 Michael Collison <michael.collison@arm.com>Michael Collison2016-11-231-0/+10
* re PR target/69176 (ICE in in final_scan_insn, at final.c:2981 on aarch64-lin...Richard Henderson2016-01-181-0/+5
* Update copyright years.Jakub Jelinek2016-01-041-1/+1
* [AArch64] Revert "Improve TLS Descriptor pattern to release RTL loop IV opt"Jiong Wang2015-09-281-3/+0
* [AArch64] Recommit correct version for improving TLS descriptor patternRamana Radhakrishnan2015-08-101-0/+3
* [AArch64] Tighten direct call pattern for sibcall to repair -fno-pltJiong Wang2015-08-061-2/+3
* Update copyright years.Jakub Jelinek2015-01-051-1/+1
* constraints.md (Usn, [...]): New constraints.Zhenqiang Chen2014-11-171-0/+5
* [AARCH64] Support tail indirect function call.Jiong Wang2014-05-231-0/+7
* Update copyright years in gcc/Richard Sandiford2014-01-021-1/+1
* AArch64 - Improve MOVI handling (3/5)Ian Bolton2013-06-041-3/+2
* AArch64 - Improve MOVI handling (2/5)Ian Bolton2013-06-041-3/+3
* [AArch64] Remove Usa constraint.Chris Schlumberger-Socha2013-05-231-5/+0
* aarch64.md (*mov<mode>_aarch64): Add alternatives for scalar move.Sofiane Naci2013-04-021-0/+16