summaryrefslogtreecommitdiff
path: root/gcc/config/aarch64/aarch64.md
Commit message (Expand)AuthorAgeFilesLines
* Add support for SVE scatter storesrsandifo2018-01-131-0/+1
* Add support for SVE gather loadsrsandifo2018-01-131-0/+1
* Add support for in-order addition reduction using SVE FADDArsandifo2018-01-131-0/+1
* Add support for conditional reductions using SVE CLASTBrsandifo2018-01-131-0/+1
* Add support for fully-predicated loopsrsandifo2018-01-131-0/+57
* SLP reductions with variable-length vectorsrsandifo2018-01-131-0/+1
* [AArch64] SVE load/store_lanes supportrsandifo2018-01-131-0/+2
* [AArch64] Add SVE supportrsandifo2018-01-131-36/+147
* [AArch64] Set NUM_POLY_INT_COEFFS to 2rsandifo2018-01-111-1/+1
* Update copyright years.jakub2018-01-031-1/+1
* [AArch64] Fix address printing on ILP32wilco2017-12-011-11/+11
* [Patch AArch64] Fixup floating point division with -march=armv8-a+nosimdramana2017-11-281-1/+1
* [AArch64] Use aarch64_reg_or_imm instead of nonmemory_operandrsandifo2017-11-071-3/+3
* [AArch64] Rename the internal "Upl" constraintrsandifo2017-11-011-2/+2
* 2017-10-26 Michael Collison <michael.collison@arm.com>collison2017-10-271-3/+29
* 2017-10-26 Tamar Christina <tamar.christina@arm.com>tnfchris2017-10-261-1/+3
* 2017-10-07 Michael Collison <michael.collison@arm.com>collison2017-10-081-0/+29
* Remove '*' from movsi/di/ti patternswilco2017-09-121-6/+6
* [Patch AArch64 2/2] Fix memory sizes to load/store patternsjgreenhalgh2017-09-121-14/+15
* [Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to enco...jgreenhalgh2017-09-121-35/+35
* [AArch64] Rename cmp_result iteratorrsandifo2017-08-311-8/+8
* [AArch64] Remove use of wider vector modesrsandifo2017-08-311-0/+3
* [AArch64] Fix label modersandifo2017-08-221-1/+1
* 2017-08-11 Tamar Christina <tamar.christina@arm.com>tnfchris2017-08-111-3/+3
* Add falkor pipeline description.wilson2017-08-091-0/+1
* 2017-08-08 Tamar Christina <tamar.christina@arm.com>tnfchris2017-08-081-0/+36
* 2017-07-28 Tamar Christina <tamar.christina@arm.com>tnfchris2017-07-281-6/+7
* 2017-07-28 Tamar Christina <tamar.christina@arm.com>tnfchris2017-07-281-26/+63
* 2017-07-28 Tamar Christina <tamar.christina@arm.com>tnfchris2017-07-281-7/+9
* [PATCH][AArch64] Fix missing optimization for CMP+ANDjgreenhalgh2017-07-271-0/+36
* 2017-07-11 Michael Collison <michael.collison@arm.com>collison2017-07-121-0/+11
* 2017-06-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>collison2017-06-291-0/+91
* Emit SIMD moves as movwilco2017-06-211-2/+2
* 2017-06-09 Tamar Christina <tamar.christina@arm.com>tnfchris2017-06-091-0/+12
* 2017-06-07 Tamar Christina <tamar.christina@arm.com>tnfchris2017-06-071-4/+6
* [AArch64] Use SUBS for parallel subtraction and comparison with immediatektkachov2017-06-051-0/+31
* [AArch64] Peephole for SUBSktkachov2017-06-051-0/+18
* [PATCH][AARCH64]Simplify call, call_value, sibcall, sibcall_value patterns.renlin2017-05-151-128/+18
* [AArch64] Tighten move constraints for symbolic operandsrsandifo2017-05-081-2/+2
* Float to int moves currently generate inefficient code due towilco2017-05-051-4/+4
* [AArch64] Accept more addressing modes for PRFMktkachov2017-05-041-10/+14
* PR target/78002ebotcazou2017-04-051-5/+5
* 2016-02-07 Andrew Pinski <apinski@cavium.com>naveenh2017-02-081-0/+33
* 2017-02-06 Julian Brown <julian@codesourcery.com>naveenh2017-02-061-0/+1
* [AArch64][1/4] Support Return address protection on AArch64jiwang2017-01-201-1/+46
* [AArch64] Purge leftover occurrences of aarch64_nopcrelative_literal_loadsktkachov2017-01-191-2/+2
* This patch simplifies the handling of EH return. We force the use of thewilco2017-01-171-19/+0
* Update copyright years.jakub2017-01-011-1/+1
* [AArch64] Split X-reg UBFIZ into W-reg LSL when possiblektkachov2016-12-161-0/+18
* [AArch64] Split X-reg UBFX into W-reg LSR when possiblektkachov2016-12-161-0/+20
View Lorry Controller Status