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path: root/gcc/config/aarch64/aarch64.c
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* * expr.h: Remove prototypes of functions defined in builtins.c.amacleod2014-06-021-0/+1
* Fix ICE in aarch64_float_const_representable_pvries2014-06-021-0/+3
* Detect EXT patterns to vec_perm_const, use for EXT intrinsicsalalaw012014-05-291-1/+67
* [AARCH64] Support tail indirect function call.mshawcroft2014-05-231-11/+4
* 2014-05-23 Kugan Vivekanandarajah <kuganv@linaro.org>kugan2014-05-221-0/+4
* 2014-05-22 Kugan Vivekanandarajah <kuganv@linaro.org>kugan2014-05-221-4/+3
* use templates instead of gengtype for typed allocation functionstbsaunde2014-05-171-1/+1
* [AArch64 costs] Fixup to costing of FNMULjgreenhalgh2014-05-161-10/+4
* [AArch64 costs 18/18] Dump a message if we are unable to cost an insn.jgreenhalgh2014-05-161-1/+5
* [AArch64 costs 17/18] Cost for SYMBOL_REF, HIGH and LO_SUMjgreenhalgh2014-05-161-6/+35
* [AArch64 costs 16/18] Cost TRUNCATEjgreenhalgh2014-05-161-0/+33
* [AArch64 costs 15/18] Cost more Floating point RTX.jgreenhalgh2014-05-161-0/+83
* [AArch64 costs 14/18] Cost comparisons, flag setting operators and IF_THEN_ELSEjgreenhalgh2014-05-161-11/+148
* [AArch64 costs 13/18] Improve costs for div/modjgreenhalgh2014-05-161-8/+7
* [AArch64 costs 12/18] Improve costs for sign/zero extractsjgreenhalgh2014-05-161-2/+61
* [AArch64 costs 11/18] Improve costs for rotate and shift operations.jgreenhalgh2014-05-161-9/+47
* [AArch64 costs 10/18] Improve costs for sign/zero extend operationsjgreenhalgh2014-05-161-6/+47
* [AArch64 costs 9/18] Better cost logical operationsjgreenhalgh2014-05-161-5/+60
* [AArch64 costs 8/18] Cost memory accesses using address costs jgreenhalgh2014-05-161-2/+30
* [AArch64 costs 7/18] Improve SET cost.jgreenhalgh2014-05-161-8/+35
* [AArch64 costs 6/18] Set default costs and handle vector modes.jgreenhalgh2014-05-161-0/+15
* [AArch64 costs 5/18] Factor out common MULT casesjgreenhalgh2014-05-161-110/+254
* [AArch64 costs 4/18] Better estimate cost of building a constantjgreenhalgh2014-05-161-12/+84
* [AArch64 costs 3/18] Wrap aarch64_rtx_costs to dump verbose outputjgreenhalgh2014-05-161-0/+21
* [AArch64 costs 2/18] Add cost tables for Cortex-A57jgreenhalgh2014-05-161-2/+43
* [AArch64 costs 1/18] Refactor aarch64_address_costs.jgreenhalgh2014-05-161-31/+104
* Implement HARD_REGNO_CALLER_SAVE_MODE for AArch64ibolton2014-05-131-0/+18
* Merge in trunk.mrs2014-05-051-1/+2
* Merge in trunk.mrs2014-04-301-1/+32
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| * [AArch64] Relax modes_tieable_p and cannot_change_mode_classjgreenhalgh2014-04-281-1/+32
* | Merge in trunk.mrs2014-04-241-7/+32
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| * [AArch64] Enable TBL for big-endian.belagod2014-04-241-5/+0
| * [AArch64] Reverse TBL indices for big-endian.belagod2014-04-241-1/+9
| * [AArch64] Fully support rotate on logical operations.mshawcroft2014-04-231-1/+5
| * [AArch64] Add handling of bswap operations in rtx costsktkachov2014-04-231-0/+8
| * [AArch64][2/3] Recognise rev16 operations on SImode and DImode dataktkachov2014-04-231-0/+10
* | Merge in trunk.mrs2014-04-221-32/+66
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| * [AArch64] Fix TLS for ILP32.mshawcroft2014-04-221-6/+42
| * [AArch64] Define TARGET_FLAGS_REGNUMmshawcroft2014-04-221-0/+3
| * [AArch64] Fix aarch64_initial_elimination_offset calculation.mshawcroft2014-04-221-6/+1
| * [AArch64] Fix indentation.mshawcroft2014-04-221-22/+22
* | Merge from trunk.rsandifo2014-04-221-18/+19
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| * [AArch64] Add a space to memory asm code between base register and offset.mshawcroft2014-04-221-14/+14
| * aarch64: Fix build error in aarch64_register_move_costrth2014-04-181-4/+5
* | Merge in trunk.mrs2014-04-021-60/+46
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| * PR target/60034kugan2014-03-301-0/+3
| * [PR 60580, AArch64] Fix __attribute__ ((optimize("no-omit-frame-pointer")))mshawcroft2014-03-271-42/+14
| * [PATCH AArch64] Fix aarch64_simd_valid_immediate for Bigendianjgreenhalgh2014-03-251-1/+3
| * * config/aarch64/aarch64.c: Correct the comments about theyufeng2014-03-181-8/+11
| * [AArch64] Fix selection of default CPU options at configure-timektkachov2014-03-121-1/+1