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path: root/gcc/config/aarch64/aarch64.c
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* Update copyright years.Jakub Jelinek2016-01-041-1/+1
* [AArch64] PR rtl-optimization/68796 Add compare-of-zero_extract patternKyrylo Tkachov2015-12-181-1/+18
* [AArch64] Properly cost zero_extend+ashift forms of ubfi[xz]Kyrylo Tkachov2015-12-161-0/+62
* [Patch AArch64] Reinstate CANNOT_CHANGE_MODE_CLASS to fix pr67609James Greenhalgh2015-12-091-0/+18
* [AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler direc...Kyrylo Tkachov2015-12-041-13/+0
* re PR middle-end/65958 (-fstack-check breaks alloca on architectures using ge...Eric Botcazou2015-12-041-0/+186
* aarch64.c (aarch64_legitimize_address): legitimize address expressions like R...Bin Cheng2015-12-041-1/+63
* Add cost model for Exynos M1Evandro Menezes2015-12-031-0/+66
* Add an rsqrt_optab and IFN_RSQRT internal functionRichard Sandiford2015-12-031-14/+35
* Fix typo in aarch64.cRamana Radhakrishnan2015-12-011-1/+1
* re PR tree-optimization/68501 (sqrt builtin is not used anymore)Jakub Jelinek2015-11-301-5/+7
* [AArch64] PR target/68363 Check that argument is real INSN in aarch64_madd_ne...Kyrylo Tkachov2015-11-231-1/+1
* [Patch AArch64] Add support for Cortex-A35James Greenhalgh2015-11-171-0/+25
* [AArch64] Cortex-A57 Choose some new branch costs.James Greenhalgh2015-11-161-1/+8
* [AArch64] Add extra tuning parameters for target processorsEvandro Menezes2015-11-121-0/+36
* Workaround PR68256 on AArch64Ramana Radhakrishnan2015-11-101-3/+5
* [AArch64][cleanup] Remove uses of CONST_DOUBLE_HIGH, CONST_DOUBLE_LOWKyrylo Tkachov2015-11-091-24/+8
* [AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INTKyrylo Tkachov2015-11-091-5/+4
* Machine modes for address printing.Julian Brown2015-11-091-16/+16
* [Patch AArch64] Switch constant pools to separate rodata sections.Ramana Radhakrishnan2015-11-061-9/+23
* aarch64-builtins.c: Builtins for rsqrt and rsqrtf.Benedikt Huber2015-11-061-2/+105
* tree-vectorizer.h (struct _bb_vec_info): Add region_begin/end members.Richard Biener2015-11-061-0/+1
* [AArch64] Handle vector float modes properly in aarch64_output_simd_mov_immed...Kyrylo Tkachov2015-10-271-1/+4
* [PATCH] [AArch64] Distinct costs for sign and zero extensionEvandro Menezes2015-10-271-5/+11
* [AArch64] Enable autoprefetcher modelling in the schedulerKyrylo Tkachov2015-10-271-0/+47
* [Patch AArch64 63304] Fix issue with global state.Ramana Radhakrishnan2015-10-221-10/+13
* [AArch64] Add support for 64-bit vector-mode ldp/stpKyrylo Tkachov2015-10-201-2/+15
* [AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisationKyrylo Tkachov2015-10-201-0/+59
* gen-mul-tables.cc: Adjust include files.Andrew MacLeod2015-10-161-27/+11
* rs6000.h (RS6000_ALIGN): Implement using ROUND_UP macro.Uros Bizjak2015-10-121-20/+20
* Remove REAL_VALUE_FROM_CONST_DOUBLERichard Sandiford2015-10-051-12/+8
* Replace REAL_VALUES_EQUAL with real_equalRichard Sandiford2015-10-051-1/+1
* [AArch64] Use default_elf_asm_named_section instead of special cased hookRamana Radhakrishnan2015-10-021-74/+0
* [AArch64] Revert "Improve TLS Descriptor pattern to release RTL loop IV opt"Jiong Wang2015-09-281-26/+8
* [AArch64] Handle const address in aarch64_print_operandJiong Wang2015-09-241-0/+1
* [AArch64] Delete aarch64_symbol_context which is not usedJiong Wang2015-09-241-19/+13
* [AArch64] Use atomic load-operate instructions for update-fetch patterns.Matthew Wahab2015-09-221-6/+66
* [AArch64] Use atomic load-operate instructions for fetch-update patterns.Matthew Wahab2015-09-221-3/+172
* [AArch64] Use atomic instructions for swap and fetch-update operations.Matthew Wahab2015-09-221-1/+45
* [AArch64][5/5] Cleanup immediate generation code in aarch64_internal_mov_imme...Wilco Dijkstra2015-09-201-98/+39
* [AArch64][4/5] Remove redundant codeWilco Dijkstra2015-09-201-60/+0
* [AArch64][3/5] Remove dead codeWilco Dijkstra2015-09-201-69/+0
* [AArch64][2/5] Improve aarch64_internal_mov_immediate by using faster algorithmWilco Dijkstra2015-09-201-73/+23
* [AArch64][1/5] Reimplement aarch64_bitmask_immWilco Dijkstra2015-09-201-9/+53
* [AArch64 array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_PAlan Lawrence2015-09-151-1/+2
* [AArch64 array_mode 4/8] Remove EImodeAlan Lawrence2015-09-151-1/+1
* [AArch64] Handle literal pools for functions > 1 MiB in size.Ramana Radhakrishnan2015-09-141-4/+105
* [AArch64][1/3] Expand signed mod by power of 2 using CSNEGKyrylo Tkachov2015-09-091-0/+19
* [AArch64] Improve code generation for float16 vector codeAlan Lawrence2015-09-081-0/+2
* [AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreateAlan Lawrence2015-09-081-0/+3
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