| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update copyright years. | jakub | 2017-01-01 | 1 | -1/+1 |
| * | 2016-11-28 Tamar Christina <tamar.christina@arm.com> | tnfchris | 2016-11-28 | 1 | -0/+1 |
| * | 2016-11-28 Tamar Christina <tamar.christina@arm.com> | tnfchris | 2016-11-28 | 1 | -0/+13 |
| * | [PATCH AArch64] Add more AArch64 NEON intrinsics | jgreenhalgh | 2016-08-02 | 1 | -11/+7 |
| * | [AArch64][9/10] ARMv8.2-A FP16 three operands scalar intrinsics | jiwang | 2016-07-25 | 1 | -0/+2 |
| * | [AArch64][8/10] ARMv8.2-A FP16 two operands scalar intrinsics | jiwang | 2016-07-25 | 1 | -11/+20 |
| * | [AArch64][7/10] ARMv8.2-A FP16 one operand scalar intrinsics | jiwang | 2016-07-25 | 1 | -10/+44 |
| * | [AArch64][6/14] ARMv8.2-A FP16 reduction vector intrinsics | jiwang | 2016-07-25 | 1 | -4/+4 |
| * | [AArch64][4/10] ARMv8.2-A FP16 three operands vector intrinsics | jiwang | 2016-07-25 | 1 | -1/+3 |
| * | [AArch64][3/10] ARMv8.2-A FP16 two operands vector intrinsics | jiwang | 2016-07-25 | 1 | -17/+23 |
| * | [AArch64][2/10] ARMv8.2-A FP16 one operand vector intrinsics | jiwang | 2016-07-25 | 1 | -11/+45 |
| * | [AArch64] Use fmin/fmax for v[min|max]nm{q} intrinsics | jiwang | 2016-07-08 | 1 | -2/+6 |
| * | [AArch64] Renaming ARMv8.1 to ARMv8.1-A in comments and documentations | jiwang | 2016-07-04 | 1 | -1/+1 |
| * | [Patch AArch64] Fixup to fcvt patterns added in r237200 | jgreenhalgh | 2016-06-20 | 1 | -4/+4 |
| * | [AArch64, 6/6] Reimplement vpadd intrinsics & extend rtl patterns to all modes | jiwang | 2016-06-08 | 1 | -0/+3 |
| * | [AArch64, 5/6] Reimplement fabd intrinsics & merge rtl patterns | jiwang | 2016-06-08 | 1 | -0/+3 |
| * | [AArch64, 4/6] Reimplement frsqrts intrinsics | jiwang | 2016-06-08 | 1 | -0/+3 |
| * | [AArch64, 3/6] Reimplement frsqrte intrinsics | jiwang | 2016-06-08 | 1 | -0/+3 |
| * | [AArch64, 2/6] Reimplement vector fixed-point intrinsics | jiwang | 2016-06-08 | 1 | -4/+4 |
| * | [AArch64, 1/6] Reimplement scalar fixed-point intrinsics | jiwang | 2016-06-08 | 1 | -0/+6 |
| * | [AArch64] Remove TODO (redundant type conversions) in arm_neon.h | jiwang | 2016-01-15 | 1 | -23/+23 |
| * | Update copyright years. | jakub | 2016-01-04 | 1 | -1/+1 |
| * | * config/aarch64/aarch64-simd-builtins.def: | mwahab | 2015-11-26 | 1 | -0/+14 |
| * | [AArch64] Fix vqtb[lx][234] on big-endian | clyon | 2015-11-06 | 1 | -2/+20 |
| * | [AARCH64][PATCH 1/3] Implementing the variants of the vmulx_ NEON intrinsic | jgreenhalgh | 2015-11-03 | 1 | -0/+1 |
| * | [AArch64_be] Fix vtbl[34] and vtbx4 | clyon | 2015-10-12 | 1 | -0/+5 |
| * | [AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix | alalaw01 | 2015-09-08 | 1 | -1/+2 |
| * | [AArch64] Implement vcvt_{,high_}f16_f32 | alalaw01 | 2015-09-08 | 1 | -1/+2 |
| * | [AArch64] Add support for float16x{4,8}_t vectors/builtins | alalaw01 | 2015-09-08 | 1 | -4/+4 |
| * | gcc/ChangeLog: | cbaylis | 2015-07-22 | 1 | -6/+6 |
| * | [AArch64] Use target builtin instead of __builtin_sqrt for vsqrt_f64 | ktkachov | 2015-02-04 | 1 | -1/+1 |
| * | [Patch AArch64] Make integer vabs intrinsics UNSPECs | jgreenhalgh | 2015-01-28 | 1 | -1/+2 |
| * | * config/aarch64/aarch64-simd.md (aarch64_<maxmin_uns>p<mode>): New | fyang | 2015-01-19 | 1 | -0/+10 |
| * | Update copyright years. | jakub | 2015-01-05 | 1 | -1/+1 |
| * | [AArch64]Remove be_checked_get_lane, check bounds with __builtin_aarch64_im_l... | alalaw01 | 2014-12-09 | 1 | -3/+0 |
| * | [AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi | alalaw01 | 2014-12-09 | 1 | -2/+0 |
| * | * config/aarch64/arm_neon.h (vrecpe_u32, vrecpeq_u32): Rewrite using | fyang | 2014-12-08 | 1 | -0/+8 |
| * | * config/aarch64/aarch64-simd.md (clrsb<mode>2, popcount<mode>2): New | fyang | 2014-12-07 | 1 | -0/+2 |
| * | 2014-12-05 Andrew Pinski <apinski@cavium.com> | pinskia | 2014-12-05 | 1 | -1/+1 |
| * | [AArch64] Remove/merge redundant iterators | alalaw01 | 2014-12-03 | 1 | -14/+14 |
| * | [AArch64] Add vector pattern for __builtin_ctz | jiwang | 2014-11-21 | 1 | -0/+1 |
| * | gcc/: | alalaw01 | 2014-11-17 | 1 | -1/+0 |
| * | Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips ... | alalaw01 | 2014-11-12 | 1 | -32/+34 |
| * | [AArch64] Use new reduc_[us](min|max)_scal optabs, inc. for builtins | alalaw01 | 2014-10-27 | 1 | -7/+7 |
| * | [AArch64] Use new reduc_plus_scal optabs, inc. for __builtins | alalaw01 | 2014-10-27 | 1 | -3/+2 |
| * | [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in... | cbaylis | 2014-10-24 | 1 | -0/+4 |
| * | PR target/63173 | fyang | 2014-10-24 | 1 | -0/+4 |
| * | [AArch64] Wire up vqdmullh_laneq_s16 and vqdmullh_laneq_s32 | jgreenhalgh | 2014-09-30 | 1 | -1/+1 |
| * | [AArch64] Simplify vreinterpret for float64x1_t using casts. | alalaw01 | 2014-09-11 | 1 | -23/+0 |
| * | [AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant la... | ktkachov | 2014-09-09 | 1 | -8/+8 |
